; generated by Component: ARM Compiler 5.05 update 2 (build 169) Tool: ArmCC [4d0f38]
; commandline ArmCC [--list --debug -c --asm --interleave -o.\obj\system_m451series.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\system_m451series.d --cpu=Cortex-M4.fp --apcs=interwork -O0 --diag_suppress=9931 -I..\..\..\Library\CMSIS\Include -I..\..\..\Library\Device\Nuvoton\M451Series\Include -I..\..\..\Library\StdDriver\inc -I..\Bsp -I..\User -I..\lcd_driver -I..\exti_driver -I..\led_driver -I..\touch -I..\dotmatix_lcd -I..\KH -ID:\\A\LCD\͹ϵ_VKL\VKL\VKL060_TESTCODE\project\VKL060_FUNC\Keil\RTE -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\4.3.0\CMSIS\Include -D__UVISION_VERSION=515 -D_RTE_ --omf_browse=.\obj\system_m451series.crf ..\..\..\Library\Device\Nuvoton\M451Series\Source\system_M451Series.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  SystemCoreClockUpdate PROC
;;;30      *----------------------------------------------------------------------------*/
;;;31     void SystemCoreClockUpdate(void)             /* Get Core Clock Frequency      */
000000  b570              PUSH     {r4-r6,lr}
;;;32     {
;;;33     #if 1
;;;34         unsigned int u32Freq, u32ClkSrc;
;;;35         unsigned int u32HclkDiv;
;;;36     
;;;37         /* Update PLL Clock */
;;;38         PllClock = CLK_GetPLLClockFreq();
000002  f7fffffe          BL       CLK_GetPLLClockFreq
000006  4941              LDR      r1,|L1.268|
000008  6008              STR      r0,[r1,#0]  ; PllClock
;;;39     
;;;40         u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
00000a  4841              LDR      r0,|L1.272|
00000c  6800              LDR      r0,[r0,#0]
00000e  f0000507          AND      r5,r0,#7
;;;41     
;;;42         if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
000012  2d02              CMP      r5,#2
000014  d102              BNE      |L1.28|
;;;43         {
;;;44             /* Use PLL clock */
;;;45             u32Freq = PllClock;
000016  4608              MOV      r0,r1
000018  6804              LDR      r4,[r0,#0]  ; PllClock
00001a  e002              B        |L1.34|
                  |L1.28|
;;;46         }
;;;47         else
;;;48         {
;;;49             /* Use the clock sources directly */
;;;50             u32Freq = gau32ClkSrcTbl[u32ClkSrc];
00001c  483d              LDR      r0,|L1.276|
00001e  f8504025          LDR      r4,[r0,r5,LSL #2]
                  |L1.34|
;;;51         }
;;;52     
;;;53         u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
000022  483b              LDR      r0,|L1.272|
000024  3010              ADDS     r0,r0,#0x10
000026  6800              LDR      r0,[r0,#0]
000028  f000000f          AND      r0,r0,#0xf
00002c  1c46              ADDS     r6,r0,#1
;;;54     
;;;55         /* Update System Core Clock */
;;;56         SystemCoreClock = u32Freq / u32HclkDiv;
00002e  fbb4f0f6          UDIV     r0,r4,r6
000032  4939              LDR      r1,|L1.280|
000034  6008              STR      r0,[r1,#0]  ; SystemCoreClock
;;;57     
;;;58     
;;;59         //if(SystemCoreClock == 0)
;;;60         //    __BKPT(0);
;;;61     
;;;62         CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
000036  4608              MOV      r0,r1
000038  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
00003a  4938              LDR      r1,|L1.284|
00003c  4408              ADD      r0,r0,r1
00003e  0049              LSLS     r1,r1,#1
000040  fbb0f0f1          UDIV     r0,r0,r1
000044  4936              LDR      r1,|L1.288|
000046  6008              STR      r0,[r1,#0]  ; CyclesPerUs
;;;63     #endif
;;;64     }
000048  bd70              POP      {r4-r6,pc}
;;;65     
                          ENDP

                  SystemInit PROC
;;;74      */
;;;75     void SystemInit(void)
00004a  bf00              NOP      
00004c  bf00              NOP      
00004e  bf00              NOP      
                  |L1.80|
000050  2059              MOVS     r0,#0x59
000052  4934              LDR      r1,|L1.292|
000054  6008              STR      r0,[r1,#0]
000056  2016              MOVS     r0,#0x16
000058  0589              LSLS     r1,r1,#22
00005a  f8c10100          STR      r0,[r1,#0x100]
00005e  2088              MOVS     r0,#0x88
000060  f8c10100          STR      r0,[r1,#0x100]
000064  06c0              LSLS     r0,r0,#27
000066  f8d00100          LDR      r0,[r0,#0x100]
00006a  2800              CMP      r0,#0
00006c  d0f0              BEQ      |L1.80|
00006e  bf00              NOP      
;;;76     {
;;;77         /* ToDo: add code to initialize the system
;;;78                  do not use global variables because this function is called before
;;;79                  reaching pre-main. RW section maybe overwritten afterwards.          */
;;;80         
;;;81         SYS_UnlockReg();
;;;82         /* One-time POR18 */
;;;83         if((SYS->PDID >> 12) == 0x945)
000070  4608              MOV      r0,r1
000072  6800              LDR      r0,[r0,#0]
000074  f6401145          MOV      r1,#0x945
000078  ebb13f10          CMP      r1,r0,LSR #12
00007c  d105              BNE      |L1.138|
;;;84         {
;;;85             M32(GCR_BASE+0x14) |= BIT7;
00007e  0788              LSLS     r0,r1,#30
000080  6940              LDR      r0,[r0,#0x14]
000082  f0400080          ORR      r0,r0,#0x80
000086  0789              LSLS     r1,r1,#30
000088  6148              STR      r0,[r1,#0x14]
                  |L1.138|
;;;86         }
;;;87         /* Force to use INV type with HXT */
;;;88         CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
00008a  4821              LDR      r0,|L1.272|
00008c  3810              SUBS     r0,r0,#0x10
00008e  6800              LDR      r0,[r0,#0]
000090  f4205080          BIC      r0,r0,#0x1000
000094  f04f4180          MOV      r1,#0x40000000
000098  f8c10200          STR      r0,[r1,#0x200]
;;;89         SYS_LockReg();
00009c  bf00              NOP      
00009e  2000              MOVS     r0,#0
0000a0  4920              LDR      r1,|L1.292|
0000a2  6008              STR      r0,[r1,#0]
0000a4  bf00              NOP      
;;;90     
;;;91     
;;;92     #ifdef EBI_INIT
;;;93         extern void SYS_Init();
;;;94         extern void EBI_Init();
;;;95         
;;;96         SYS_UnlockReg();
;;;97         SYS_Init();
;;;98         EBI_Init();
;;;99         SYS_LockReg();
;;;100    #endif
;;;101    
;;;102        /* FPU settings ------------------------------------------------------------*/
;;;103    #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
;;;104        SCB->CPACR |= ((3UL << 10 * 2) |               /* set CP10 Full Access */
0000a6  4820              LDR      r0,|L1.296|
0000a8  6800              LDR      r0,[r0,#0]
0000aa  f4400070          ORR      r0,r0,#0xf00000
0000ae  491e              LDR      r1,|L1.296|
0000b0  6008              STR      r0,[r1,#0]
;;;105                       (3UL << 11 * 2));               /* set CP11 Full Access */
;;;106    #endif
;;;107    
;;;108    }
0000b2  4770              BX       lr
;;;109    /*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
                          ENDP

                  CLK_GetPLLClockFreq PROC
;;;357      */
;;;358    __STATIC_INLINE unsigned int CLK_GetPLLClockFreq(void)
0000b4  b5f8              PUSH     {r3-r7,lr}
;;;359    {
;;;360        unsigned int u32PllFreq = 0, u32PllReg;
0000b6  2600              MOVS     r6,#0
;;;361        unsigned int u32FIN, u32NF, u32NR, u32NO;
;;;362        unsigned char au8NoTbl[4] = {1, 2, 2, 4};
0000b8  a01c              ADR      r0,|L1.300|
0000ba  6800              LDR      r0,[r0,#0]
0000bc  9000              STR      r0,[sp,#0]
;;;363    
;;;364        u32PllReg = CLK->PLLCTL;
0000be  4814              LDR      r0,|L1.272|
0000c0  3030              ADDS     r0,r0,#0x30
0000c2  6801              LDR      r1,[r0,#0]
;;;365    
;;;366        if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk))
0000c4  f40120a0          AND      r0,r1,#0x50000
0000c8  b108              CBZ      r0,|L1.206|
;;;367            return 0;           /* PLL is in power down mode or fix low */
0000ca  2000              MOVS     r0,#0
                  |L1.204|
;;;368    
;;;369        if(u32PllReg & CLK_PLLCTL_PLLSRC_HIRC)
;;;370            u32FIN = __HIRC;    /* PLL source clock from HIRC */
;;;371        else
;;;372            u32FIN = __HXT;     /* PLL source clock from HXT */
;;;373    
;;;374        if(u32PllReg & CLK_PLLCTL_BP_Msk)
;;;375            return u32FIN;      /* PLL is in bypass mode */
;;;376    
;;;377        /* PLL is output enabled in normal work mode */
;;;378        u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
;;;379        u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2;
;;;380        u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 2;
;;;381    
;;;382        /* u32FIN is shifted 2 bits to avoid overflow */
;;;383        u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2);
;;;384    
;;;385        return u32PllFreq;
;;;386    }
0000cc  bdf8              POP      {r3-r7,pc}
                  |L1.206|
0000ce  f4012000          AND      r0,r1,#0x80000        ;369
0000d2  b108              CBZ      r0,|L1.216|
0000d4  4a16              LDR      r2,|L1.304|
0000d6  e000              B        |L1.218|
                  |L1.216|
0000d8  4a16              LDR      r2,|L1.308|
                  |L1.218|
0000da  f4013000          AND      r0,r1,#0x20000        ;374
0000de  b108              CBZ      r0,|L1.228|
0000e0  4610              MOV      r0,r2                 ;375
0000e2  e7f3              B        |L1.204|
                  |L1.228|
0000e4  f3c13781          UBFX     r7,r1,#14,#2          ;378
0000e8  f81d4007          LDRB     r4,[sp,r7]            ;378
0000ec  f3c10008          UBFX     r0,r1,#0,#9           ;379
0000f0  1c83              ADDS     r3,r0,#2              ;379
0000f2  f3c12044          UBFX     r0,r1,#9,#5           ;380
0000f6  1c85              ADDS     r5,r0,#2              ;380
0000f8  0890              LSRS     r0,r2,#2              ;383
0000fa  4358              MULS     r0,r3,r0              ;383
0000fc  fb15f704          SMULBB   r7,r5,r4              ;383
000100  fbb0f0f7          UDIV     r0,r0,r7              ;383
000104  0086              LSLS     r6,r0,#2              ;383
000106  4630              MOV      r0,r6                 ;385
000108  e7e0              B        |L1.204|
;;;387    
                          ENDP

00010a  0000              DCW      0x0000
                  |L1.268|
                          DCD      PllClock
                  |L1.272|
                          DCD      0x40000210
                  |L1.276|
                          DCD      gau32ClkSrcTbl
                  |L1.280|
                          DCD      SystemCoreClock
                  |L1.284|
                          DCD      0x0007a120
                  |L1.288|
                          DCD      CyclesPerUs
                  |L1.292|
                          DCD      0x40000100
                  |L1.296|
                          DCD      0xe000ed88
                  |L1.300|
00012c  01020204          DCB      1,2,2,4
                  |L1.304|
                          DCD      0x01518000
                  |L1.308|
                          DCD      0x00b71b00

                          AREA ||.data||, DATA, ALIGN=2

                  SystemCoreClock
                          DCD      0x00b71b00
                  CyclesPerUs
                          DCD      0x0000000c
                  PllClock
                          DCD      0x00b71b00
                  gau32ClkSrcTbl
                          DCD      0x00b71b00
                          DCD      0x00008000
                          DCD      0x00000000
                          DCD      0x00002710
                          DCD      0x00000000
                          DCD      0x00000000
                          DCD      0x00000000
                          DCD      0x01518000

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\Library\\Device\\Nuvoton\\M451Series\\Source\\system_M451Series.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___19_system_M451Series_c_5d646a67____REV16|
#line 114 "..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___19_system_M451Series_c_5d646a67____REV16| PROC
#line 115

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___19_system_M451Series_c_5d646a67____REVSH|
#line 128
|__asm___19_system_M451Series_c_5d646a67____REVSH| PROC
#line 129

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
