; generated by Component: ARM Compiler 5.05 update 2 (build 169) Tool: ArmCC [4d0f38]
; commandline ArmCC [--list --debug -c --asm --interleave -o.\obj\vkl128_io_i2c_dir.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\vkl128_io_i2c_dir.d --cpu=Cortex-M4.fp --apcs=interwork -O0 --diag_suppress=9931 -I..\..\..\Library\CMSIS\Include -I..\..\..\Library\Device\Nuvoton\M451Series\Include -I..\..\..\Library\StdDriver\inc -I..\Bsp -I..\User -I..\lcd_driver -I..\exti_driver -I..\led_driver -I..\touch -I..\dotmatix_lcd -I..\KH -IC:\Users\Administator\Desktop\͹ϵ_VKL\VKL\VKL128_TESTCODE\project\VKL144_FUNC\Keil\RTE -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\4.3.0\CMSIS\Include -D__UVISION_VERSION=515 -D_RTE_ --omf_browse=.\obj\vkl128_io_i2c_dir.crf ..\lcd_driver\VKL128_IO_I2C_DIR.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  Delay_nuS PROC
;;;35     *******************************************************************************/
;;;36     void Delay_nuS(unsigned int n)	   
000000  e007              B        |L1.18|
                  |L1.2|
;;;37     {
;;;38     	unsigned char i;
;;;39     	while(n--)
;;;40     	{
;;;41     		i=10;
000002  210a              MOVS     r1,#0xa
;;;42     		while(i--)
000004  e000              B        |L1.8|
                  |L1.6|
;;;43     		{//nopָݵƬӦ޸
;;;44     			__nop();
000006  bf00              NOP      
                  |L1.8|
000008  000a              MOVS     r2,r1                 ;42
00000a  f1a10301          SUB      r3,r1,#1              ;42
00000e  b2d9              UXTB     r1,r3                 ;42
000010  d1f9              BNE      |L1.6|
                  |L1.18|
000012  0002              MOVS     r2,r0                 ;39
000014  f1a00001          SUB      r0,r0,#1              ;39
000018  d1f3              BNE      |L1.2|
;;;45     		}
;;;46     	}
;;;47     }
00001a  4770              BX       lr
;;;48     /*******************************************************************************
                          ENDP

                  Delay_nmS PROC
;;;54     *******************************************************************************/
;;;55     void Delay_nmS(unsigned long int n)
00001c  b510              PUSH     {r4,lr}
;;;56     {
00001e  4604              MOV      r4,r0
;;;57     	while(n--)
000020  e003              B        |L1.42|
                  |L1.34|
;;;58     	{
;;;59     		Delay_nuS(1000);
000022  f44f707a          MOV      r0,#0x3e8
000026  f7fffffe          BL       Delay_nuS
                  |L1.42|
00002a  0020              MOVS     r0,r4                 ;57
00002c  f1a40401          SUB      r4,r4,#1              ;57
000030  d1f7              BNE      |L1.34|
;;;60     	}
;;;61     }
000032  bd10              POP      {r4,pc}
;;;62     /*******************************************************************************
                          ENDP

                  VKL128_I2CStart PROC
;;;68     *******************************************************************************/
;;;69     void VKL128_I2CStart( void )
000034  b500              PUSH     {lr}
;;;70     {
;;;71       VKL128_SCL_H();
000036  2001              MOVS     r0,#1
000038  49fe              LDR      r1,|L1.1076|
00003a  6008              STR      r0,[r1,#0]
;;;72       VKL128_SDA_H();
00003c  49fd              LDR      r1,|L1.1076|
00003e  3928              SUBS     r1,r1,#0x28
000040  6008              STR      r0,[r1,#0]
;;;73       Delay_nuS(VKL128_CLK);
000042  200a              MOVS     r0,#0xa
000044  f7fffffe          BL       Delay_nuS
;;;74       VKL128_SDA_L();
000048  2000              MOVS     r0,#0
00004a  49fa              LDR      r1,|L1.1076|
00004c  3928              SUBS     r1,r1,#0x28
00004e  6008              STR      r0,[r1,#0]
;;;75       Delay_nuS(VKL128_CLK);
000050  200a              MOVS     r0,#0xa
000052  f7fffffe          BL       Delay_nuS
;;;76     }
000056  bd00              POP      {pc}
;;;77     /*******************************************************************************
                          ENDP

                  VKL128_I2CStop PROC
;;;83     *******************************************************************************/
;;;84     void VKL128_I2CStop( void )
000058  b500              PUSH     {lr}
;;;85     {
;;;86       VKL128_SCL_H();
00005a  2001              MOVS     r0,#1
00005c  49f5              LDR      r1,|L1.1076|
00005e  6008              STR      r0,[r1,#0]
;;;87       VKL128_SDA_L();
000060  2000              MOVS     r0,#0
000062  49f4              LDR      r1,|L1.1076|
000064  3928              SUBS     r1,r1,#0x28
000066  6008              STR      r0,[r1,#0]
;;;88       Delay_nuS(VKL128_CLK);
000068  200a              MOVS     r0,#0xa
00006a  f7fffffe          BL       Delay_nuS
;;;89       VKL128_SDA_H();
00006e  2001              MOVS     r0,#1
000070  49f0              LDR      r1,|L1.1076|
000072  3928              SUBS     r1,r1,#0x28
000074  6008              STR      r0,[r1,#0]
;;;90       Delay_nuS(VKL128_CLK);
000076  200a              MOVS     r0,#0xa
000078  f7fffffe          BL       Delay_nuS
;;;91     }
00007c  bd00              POP      {pc}
;;;92     /*******************************************************************************
                          ENDP

                  VKL128_I2CSlaveAck PROC
;;;98     *******************************************************************************/
;;;99     unsigned char VKL128_I2CSlaveAck( void )
00007e  b570              PUSH     {r4-r6,lr}
;;;100    {
;;;101      unsigned int TimeOut;
;;;102      unsigned char RetValue;
;;;103    	
;;;104    	VKL128_SET_SDA_IN();
000080  2200              MOVS     r2,#0
000082  2120              MOVS     r1,#0x20
000084  48ec              LDR      r0,|L1.1080|
000086  f7fffffe          BL       GPIO_SetMode
;;;105    	//VKL128_SDA_H();	
;;;106    	VKL128_SDA_L();	//SDAΪЩƬ1ЩƬ0
00008a  2000              MOVS     r0,#0
00008c  49e9              LDR      r1,|L1.1076|
00008e  3928              SUBS     r1,r1,#0x28
000090  6008              STR      r0,[r1,#0]
;;;107      VKL128_SCL_L();
000092  49e8              LDR      r1,|L1.1076|
000094  6008              STR      r0,[r1,#0]
;;;108      Delay_nuS(VKL128_CLK);
000096  200a              MOVS     r0,#0xa
000098  f7fffffe          BL       Delay_nuS
;;;109      VKL128_SCL_H();//9SCLʱ
00009c  2001              MOVS     r0,#1
00009e  49e5              LDR      r1,|L1.1076|
0000a0  6008              STR      r0,[r1,#0]
;;;110      TimeOut = 10000;
0000a2  f2427510          MOV      r5,#0x2710
;;;111      while( TimeOut-- > 0 )
0000a6  e007              B        |L1.184|
                  |L1.168|
;;;112      {
;;;113        if( VKL128_GET_SDA()!=0 )//ȡack
0000a8  48e2              LDR      r0,|L1.1076|
0000aa  3828              SUBS     r0,r0,#0x28
0000ac  6800              LDR      r0,[r0,#0]
0000ae  b108              CBZ      r0,|L1.180|
;;;114        {
;;;115          RetValue = 1;
0000b0  2401              MOVS     r4,#1
0000b2  e001              B        |L1.184|
                  |L1.180|
;;;116        }
;;;117        else
;;;118        {
;;;119          RetValue = 0;
0000b4  2400              MOVS     r4,#0
;;;120          break;
0000b6  e003              B        |L1.192|
                  |L1.184|
0000b8  0028              MOVS     r0,r5                 ;111
0000ba  f1a50501          SUB      r5,r5,#1              ;111
0000be  d1f3              BNE      |L1.168|
                  |L1.192|
0000c0  bf00              NOP      
;;;121        }
;;;122      } 
;;;123    	VKL128_SCL_L(); //һʱΪ,ݻSTOPźš
0000c2  2000              MOVS     r0,#0
0000c4  49db              LDR      r1,|L1.1076|
0000c6  6008              STR      r0,[r1,#0]
;;;124      VKL128_SET_SDA_OUT();
0000c8  2201              MOVS     r2,#1
0000ca  2120              MOVS     r1,#0x20
0000cc  48da              LDR      r0,|L1.1080|
0000ce  f7fffffe          BL       GPIO_SetMode
;;;125      return RetValue;
0000d2  4620              MOV      r0,r4
;;;126    }
0000d4  bd70              POP      {r4-r6,pc}
;;;127    /*******************************************************************************
                          ENDP

                  VKL128_I2CSendAck PROC
;;;133    *******************************************************************************/
;;;134    void VKL128_I2CSendAck( void )
0000d6  b500              PUSH     {lr}
;;;135    {
;;;136      VKL128_SCL_L();
0000d8  2000              MOVS     r0,#0
0000da  49d6              LDR      r1,|L1.1076|
0000dc  6008              STR      r0,[r1,#0]
;;;137      VKL128_SDA_L();
0000de  49d5              LDR      r1,|L1.1076|
0000e0  3928              SUBS     r1,r1,#0x28
0000e2  6008              STR      r0,[r1,#0]
;;;138      Delay_nuS(VKL128_CLK*2);
0000e4  2014              MOVS     r0,#0x14
0000e6  f7fffffe          BL       Delay_nuS
;;;139      VKL128_SCL_H();
0000ea  2001              MOVS     r0,#1
0000ec  49d1              LDR      r1,|L1.1076|
0000ee  6008              STR      r0,[r1,#0]
;;;140      Delay_nuS(VKL128_CLK*2);
0000f0  2014              MOVS     r0,#0x14
0000f2  f7fffffe          BL       Delay_nuS
;;;141      VKL128_SCL_L();
0000f6  2000              MOVS     r0,#0
0000f8  49ce              LDR      r1,|L1.1076|
0000fa  6008              STR      r0,[r1,#0]
;;;142      VKL128_SDA_H();
0000fc  2001              MOVS     r0,#1
0000fe  49cd              LDR      r1,|L1.1076|
000100  3928              SUBS     r1,r1,#0x28
000102  6008              STR      r0,[r1,#0]
;;;143    }
000104  bd00              POP      {pc}
;;;144    /*******************************************************************************
                          ENDP

                  VKL128_I2CSendNAck PROC
;;;150    *******************************************************************************/
;;;151    void VKL128_I2CSendNAck( void )
000106  b500              PUSH     {lr}
;;;152    {
;;;153      VKL128_SCL_L();
000108  2000              MOVS     r0,#0
00010a  49ca              LDR      r1,|L1.1076|
00010c  6008              STR      r0,[r1,#0]
;;;154      VKL128_SDA_H();
00010e  2001              MOVS     r0,#1
000110  49c8              LDR      r1,|L1.1076|
000112  3928              SUBS     r1,r1,#0x28
000114  6008              STR      r0,[r1,#0]
;;;155      Delay_nuS(VKL128_CLK);
000116  200a              MOVS     r0,#0xa
000118  f7fffffe          BL       Delay_nuS
;;;156      VKL128_SCL_H();
00011c  2001              MOVS     r0,#1
00011e  49c5              LDR      r1,|L1.1076|
000120  6008              STR      r0,[r1,#0]
;;;157      Delay_nuS(VKL128_CLK);
000122  200a              MOVS     r0,#0xa
000124  f7fffffe          BL       Delay_nuS
;;;158    }
000128  bd00              POP      {pc}
;;;159    /*******************************************************************************
                          ENDP

                  VKL128_I2CWRCmd PROC
;;;165    *******************************************************************************/
;;;166    void VKL128_I2CWRCmd( unsigned char cmd )
00012a  b530              PUSH     {r4,r5,lr}
;;;167    {
00012c  4604              MOV      r4,r0
;;;168    	unsigned char i=8;
00012e  2508              MOVS     r5,#8
;;;169    	
;;;170    	while (i--)
000130  e019              B        |L1.358|
                  |L1.306|
;;;171    	{ 
;;;172    		VKL128_SCL_L();
000132  2000              MOVS     r0,#0
000134  49bf              LDR      r1,|L1.1076|
000136  6008              STR      r0,[r1,#0]
;;;173    		if(cmd&0x80)
000138  f0040080          AND      r0,r4,#0x80
00013c  b120              CBZ      r0,|L1.328|
;;;174    			VKL128_SDA_H();
00013e  2001              MOVS     r0,#1
000140  49bc              LDR      r1,|L1.1076|
000142  3928              SUBS     r1,r1,#0x28
000144  6008              STR      r0,[r1,#0]
000146  e003              B        |L1.336|
                  |L1.328|
;;;175    		else
;;;176    			VKL128_SDA_L();
000148  2000              MOVS     r0,#0
00014a  49ba              LDR      r1,|L1.1076|
00014c  3928              SUBS     r1,r1,#0x28
00014e  6008              STR      r0,[r1,#0]
                  |L1.336|
;;;177    		cmd<<=1; 
000150  0660              LSLS     r0,r4,#25
000152  0e04              LSRS     r4,r0,#24
;;;178    		Delay_nuS(VKL128_CLK);
000154  200a              MOVS     r0,#0xa
000156  f7fffffe          BL       Delay_nuS
;;;179    		VKL128_SCL_H();     
00015a  2001              MOVS     r0,#1
00015c  49b5              LDR      r1,|L1.1076|
00015e  6008              STR      r0,[r1,#0]
;;;180    		Delay_nuS(VKL128_CLK);
000160  200a              MOVS     r0,#0xa
000162  f7fffffe          BL       Delay_nuS
                  |L1.358|
000166  0028              MOVS     r0,r5                 ;170
000168  f1a50101          SUB      r1,r5,#1              ;170
00016c  b2cd              UXTB     r5,r1                 ;170
00016e  d1e0              BNE      |L1.306|
;;;181    	}
;;;182    }
000170  bd30              POP      {r4,r5,pc}
;;;183    /*******************************************************************************
                          ENDP

                  VKL128_I2CWRDat PROC
;;;189    *******************************************************************************/
;;;190    void VKL128_I2CWRDat( unsigned char dat )
000172  b530              PUSH     {r4,r5,lr}
;;;191    {
000174  4604              MOV      r4,r0
;;;192    	unsigned char i=8;
000176  2508              MOVS     r5,#8
;;;193    	while (i--)
000178  e018              B        |L1.428|
                  |L1.378|
;;;194    	{ 
;;;195    		VKL128_SCL_L();
00017a  2000              MOVS     r0,#0
00017c  49ad              LDR      r1,|L1.1076|
00017e  6008              STR      r0,[r1,#0]
;;;196    		if(dat&0x01)
000180  f0040001          AND      r0,r4,#1
000184  b120              CBZ      r0,|L1.400|
;;;197    			VKL128_SDA_H();
000186  2001              MOVS     r0,#1
000188  49aa              LDR      r1,|L1.1076|
00018a  3928              SUBS     r1,r1,#0x28
00018c  6008              STR      r0,[r1,#0]
00018e  e003              B        |L1.408|
                  |L1.400|
;;;198    		else
;;;199    			VKL128_SDA_L();
000190  2000              MOVS     r0,#0
000192  49a8              LDR      r1,|L1.1076|
000194  3928              SUBS     r1,r1,#0x28
000196  6008              STR      r0,[r1,#0]
                  |L1.408|
;;;200    		dat>>=1; 
000198  1064              ASRS     r4,r4,#1
;;;201    		Delay_nuS(VKL128_CLK);
00019a  200a              MOVS     r0,#0xa
00019c  f7fffffe          BL       Delay_nuS
;;;202    		VKL128_SCL_H();     
0001a0  2001              MOVS     r0,#1
0001a2  49a4              LDR      r1,|L1.1076|
0001a4  6008              STR      r0,[r1,#0]
;;;203    		Delay_nuS(VKL128_CLK);
0001a6  200a              MOVS     r0,#0xa
0001a8  f7fffffe          BL       Delay_nuS
                  |L1.428|
0001ac  0028              MOVS     r0,r5                 ;193
0001ae  f1a50101          SUB      r1,r5,#1              ;193
0001b2  b2cd              UXTB     r5,r1                 ;193
0001b4  d1e1              BNE      |L1.378|
;;;204    	}
;;;205    }
0001b6  bd30              POP      {r4,r5,pc}
;;;206    
                          ENDP

                  VKL128_I2CRDDat PROC
;;;213    *******************************************************************************/
;;;214    unsigned char VKL128_I2CRDDat( void )
0001b8  b570              PUSH     {r4-r6,lr}
;;;215    {
;;;216    	unsigned char i,RetValue;
;;;217    	
;;;218    	VKL128_SET_SDA_IN();
0001ba  2200              MOVS     r2,#0
0001bc  2120              MOVS     r1,#0x20
0001be  489e              LDR      r0,|L1.1080|
0001c0  f7fffffe          BL       GPIO_SetMode
;;;219    	//VKL128_SDA_H();	
;;;220    	VKL128_SDA_L();	//SDAΪЩƬ1ЩƬ0
0001c4  2000              MOVS     r0,#0
0001c6  499b              LDR      r1,|L1.1076|
0001c8  3928              SUBS     r1,r1,#0x28
0001ca  6008              STR      r0,[r1,#0]
;;;221    	RetValue=0;	
0001cc  2400              MOVS     r4,#0
;;;222      for( i=0; i<8; i++ )
0001ce  2500              MOVS     r5,#0
0001d0  e014              B        |L1.508|
                  |L1.466|
;;;223      {
;;;224    		RetValue>>=1; 
0001d2  1064              ASRS     r4,r4,#1
;;;225    		VKL128_SCL_L();     
0001d4  2000              MOVS     r0,#0
0001d6  4997              LDR      r1,|L1.1076|
0001d8  6008              STR      r0,[r1,#0]
;;;226    		Delay_nuS(VKL128_CLK);
0001da  200a              MOVS     r0,#0xa
0001dc  f7fffffe          BL       Delay_nuS
;;;227    		VKL128_SCL_H();
0001e0  2001              MOVS     r0,#1
0001e2  4994              LDR      r1,|L1.1076|
0001e4  6008              STR      r0,[r1,#0]
;;;228    		Delay_nuS(VKL128_CLK);
0001e6  200a              MOVS     r0,#0xa
0001e8  f7fffffe          BL       Delay_nuS
;;;229    		if( VKL128_GET_SDA()!=0 )
0001ec  4891              LDR      r0,|L1.1076|
0001ee  3828              SUBS     r0,r0,#0x28
0001f0  6800              LDR      r0,[r0,#0]
0001f2  b108              CBZ      r0,|L1.504|
;;;230    			RetValue|=0x80;
0001f4  f0440480          ORR      r4,r4,#0x80
                  |L1.504|
0001f8  1c68              ADDS     r0,r5,#1              ;222
0001fa  b2c5              UXTB     r5,r0                 ;222
                  |L1.508|
0001fc  2d08              CMP      r5,#8                 ;222
0001fe  dbe8              BLT      |L1.466|
;;;231    	}
;;;232      VKL128_SET_SDA_OUT();
000200  2201              MOVS     r2,#1
000202  2120              MOVS     r1,#0x20
000204  488c              LDR      r0,|L1.1080|
000206  f7fffffe          BL       GPIO_SetMode
;;;233      return RetValue;
00020a  4620              MOV      r0,r4
;;;234    }
00020c  bd70              POP      {r4-r6,pc}
;;;235    /*******************************************************************************
                          ENDP

                  WriteCmdVKL128 PROC
;;;241    *******************************************************************************/
;;;242    unsigned char  WriteCmdVKL128(unsigned char cmd)
00020e  b510              PUSH     {r4,lr}
;;;243    {
000210  4604              MOV      r4,r0
;;;244    	//STARTź	
;;;245    	VKL128_I2CStart(); 									
000212  f7fffffe          BL       VKL128_I2CStart
;;;246    	//SLAVEַ
;;;247    	VKL128_I2CWRCmd(VKL128_ADDRWR); 	
000216  207c              MOVS     r0,#0x7c
000218  f7fffffe          BL       VKL128_I2CWRCmd
;;;248    	if( 1 == VKL128_I2CSlaveAck() )
00021c  f7fffffe          BL       VKL128_I2CSlaveAck
000220  2801              CMP      r0,#1
000222  d103              BNE      |L1.556|
;;;249    	{
;;;250    		VKL128_I2CStop();													
000224  f7fffffe          BL       VKL128_I2CStop
;;;251    		return 0;										
000228  2000              MOVS     r0,#0
                  |L1.554|
;;;252    	}
;;;253    	
;;;254    	VKL128_I2CWRCmd(cmd); 						
;;;255    	if( 1 == VKL128_I2CSlaveAck() )
;;;256    	{
;;;257    		VKL128_I2CStop();													
;;;258    		return 0;
;;;259    	}
;;;260    	//STOPź
;;;261    	 VKL128_I2CStop();											
;;;262    	 return 0;    
;;;263    }
00022a  bd10              POP      {r4,pc}
                  |L1.556|
00022c  4620              MOV      r0,r4                 ;254
00022e  f7fffffe          BL       VKL128_I2CWRCmd
000232  f7fffffe          BL       VKL128_I2CSlaveAck
000236  2801              CMP      r0,#1                 ;255
000238  d103              BNE      |L1.578|
00023a  f7fffffe          BL       VKL128_I2CStop
00023e  2000              MOVS     r0,#0                 ;258
000240  e7f3              B        |L1.554|
                  |L1.578|
000242  f7fffffe          BL       VKL128_I2CStop
000246  2000              MOVS     r0,#0                 ;262
000248  e7ef              B        |L1.554|
;;;264    /*******************************************************************************
                          ENDP

                  WritenDataVKL128 PROC
;;;272    *******************************************************************************/
;;;273    unsigned char  WritenDataVKL128(unsigned char Addr,unsigned char *Databuf,unsigned char Cnt)
00024a  e92d41f0          PUSH     {r4-r8,lr}
;;;274    {
00024e  4606              MOV      r6,r0
000250  460c              MOV      r4,r1
000252  4617              MOV      r7,r2
;;;275    	unsigned char n;
;;;276    	
;;;277    	//STARTź	
;;;278    	VKL128_I2CStart(); 									
000254  f7fffffe          BL       VKL128_I2CStart
;;;279    	//SLAVEַ
;;;280    	VKL128_I2CWRCmd(VKL128_ADDRWR); 	
000258  207c              MOVS     r0,#0x7c
00025a  f7fffffe          BL       VKL128_I2CWRCmd
;;;281    	if( 1 == VKL128_I2CSlaveAck() )
00025e  f7fffffe          BL       VKL128_I2CSlaveAck
000262  2801              CMP      r0,#1
000264  d104              BNE      |L1.624|
;;;282    	{
;;;283    		VKL128_I2CStop();													
000266  f7fffffe          BL       VKL128_I2CStop
;;;284    		return 0;										
00026a  2000              MOVS     r0,#0
                  |L1.620|
;;;285    	}
;;;286    	//ʾRAMʼַ
;;;287      //ѡڲʱӣOSCIţVKL128_ADDRWR5 bit0һҪ0
;;;288    	//ѡⲿʱӣOSCIţVKL128_ADDRWR5 bit0һҪ1                             
;;;289    	VKL128_I2CWRCmd(VKL128_ADDR5_0); 
;;;290    	if( 1 == VKL128_I2CSlaveAck() )
;;;291    	{
;;;292    		VKL128_I2CStop();													
;;;293    		return 0; 
;;;294    	}
;;;295    	VKL128_I2CWRCmd(Addr&0x1f); 						
;;;296    	if( 1 == VKL128_I2CSlaveAck() )
;;;297    	{
;;;298    		VKL128_I2CStop();													
;;;299    		return 0;
;;;300    	}
;;;301    	//CntݵʾRAM
;;;302    	for(n=0;n<Cnt;n++)
;;;303    	{ 
;;;304    		VKL128_I2CWRDat(*Databuf++);
;;;305    		if( VKL128_I2CSlaveAck()==1 )
;;;306    		{
;;;307    			VKL128_I2CStop();													
;;;308    			return 0;
;;;309    		}
;;;310    	}
;;;311    	//STOPź
;;;312    	 VKL128_I2CStop();											
;;;313    	 return 0;    
;;;314    }
00026c  e8bd81f0          POP      {r4-r8,pc}
                  |L1.624|
000270  20e8              MOVS     r0,#0xe8              ;289
000272  f7fffffe          BL       VKL128_I2CWRCmd
000276  f7fffffe          BL       VKL128_I2CSlaveAck
00027a  2801              CMP      r0,#1                 ;290
00027c  d103              BNE      |L1.646|
00027e  f7fffffe          BL       VKL128_I2CStop
000282  2000              MOVS     r0,#0                 ;293
000284  e7f2              B        |L1.620|
                  |L1.646|
000286  f006001f          AND      r0,r6,#0x1f           ;295
00028a  f7fffffe          BL       VKL128_I2CWRCmd
00028e  f7fffffe          BL       VKL128_I2CSlaveAck
000292  2801              CMP      r0,#1                 ;296
000294  d103              BNE      |L1.670|
000296  f7fffffe          BL       VKL128_I2CStop
00029a  2000              MOVS     r0,#0                 ;299
00029c  e7e6              B        |L1.620|
                  |L1.670|
00029e  2500              MOVS     r5,#0                 ;302
0002a0  e00d              B        |L1.702|
                  |L1.674|
0002a2  f8140b01          LDRB     r0,[r4],#1            ;304
0002a6  f7fffffe          BL       VKL128_I2CWRDat
0002aa  f7fffffe          BL       VKL128_I2CSlaveAck
0002ae  2801              CMP      r0,#1                 ;305
0002b0  d103              BNE      |L1.698|
0002b2  f7fffffe          BL       VKL128_I2CStop
0002b6  2000              MOVS     r0,#0                 ;308
0002b8  e7d8              B        |L1.620|
                  |L1.698|
0002ba  1c68              ADDS     r0,r5,#1              ;302
0002bc  b2c5              UXTB     r5,r0                 ;302
                  |L1.702|
0002be  42bd              CMP      r5,r7                 ;302
0002c0  dbef              BLT      |L1.674|
0002c2  f7fffffe          BL       VKL128_I2CStop
0002c6  2000              MOVS     r0,#0                 ;313
0002c8  e7d0              B        |L1.620|
;;;315    
                          ENDP

                  ReadnDataVKL128 PROC
;;;324    *******************************************************************************/
;;;325    unsigned char  ReadnDataVKL128(unsigned char Addr,unsigned char *Databuf,unsigned char Cnt)
0002ca  e92d41f0          PUSH     {r4-r8,lr}
;;;326    {
0002ce  4606              MOV      r6,r0
0002d0  460c              MOV      r4,r1
0002d2  4617              MOV      r7,r2
;;;327    	unsigned char n;
;;;328    	
;;;329    	//STARTź	
;;;330    	VKL128_I2CStart(); 									
0002d4  f7fffffe          BL       VKL128_I2CStart
;;;331    	//SLAVEַд
;;;332    	VKL128_I2CWRCmd(VKL128_ADDRWR); 	
0002d8  207c              MOVS     r0,#0x7c
0002da  f7fffffe          BL       VKL128_I2CWRCmd
;;;333    	if( 1 == VKL128_I2CSlaveAck() )
0002de  f7fffffe          BL       VKL128_I2CSlaveAck
0002e2  2801              CMP      r0,#1
0002e4  d104              BNE      |L1.752|
;;;334    	{
;;;335    		VKL128_I2CStop();													
0002e6  f7fffffe          BL       VKL128_I2CStop
;;;336    		return 0;										
0002ea  2000              MOVS     r0,#0
                  |L1.748|
;;;337    	}
;;;338    	//ʾRAMʼַ
;;;339    	//ѡڲʱӣOSCIţVKL128_ADDRWR5 bit0һҪ0
;;;340     	//ѡⲿʱӣOSCIţVKL128_ADDRWR5 bit0һҪ1
;;;341      VKL128_I2CWRCmd(VKL128_ADDR5_0); 
;;;342    	if( 1 == VKL128_I2CSlaveAck() )
;;;343    	{
;;;344    		VKL128_I2CStop();													
;;;345    		return 0; 
;;;346    	}
;;;347    	VKL128_I2CWRCmd(Addr&0x1f); 						
;;;348    	if( 1 == VKL128_I2CSlaveAck() )
;;;349    	{
;;;350    		VKL128_I2CStop();													
;;;351    		return 0;
;;;352    	}
;;;353    	//STOPź
;;;354    	 VKL128_I2CStop();	
;;;355    	//STARTź	
;;;356    	VKL128_I2CStart(); 									
;;;357    	//SLAVEַ
;;;358    	VKL128_I2CWRCmd(VKL128_ADDRRD); 	
;;;359    	if( 1 == VKL128_I2CSlaveAck() )
;;;360    	{
;;;361    		VKL128_I2CStop();													
;;;362    		return 0;										
;;;363    	}	
;;;364    	//CntݵʾRAM
;;;365    	for(n=0;n<Cnt-1;n++)
;;;366    	{ 
;;;367    		*Databuf++=VKL128_I2CRDDat();
;;;368    		VKL128_I2CSendAck();
;;;369    	}
;;;370    	*Databuf++=VKL128_I2CRDDat();
;;;371    	VKL128_I2CSendNAck();
;;;372    	//STOPź
;;;373    	 VKL128_I2CStop();											
;;;374    	 return 0;    
;;;375    }
0002ec  e8bd81f0          POP      {r4-r8,pc}
                  |L1.752|
0002f0  20e8              MOVS     r0,#0xe8              ;341
0002f2  f7fffffe          BL       VKL128_I2CWRCmd
0002f6  f7fffffe          BL       VKL128_I2CSlaveAck
0002fa  2801              CMP      r0,#1                 ;342
0002fc  d103              BNE      |L1.774|
0002fe  f7fffffe          BL       VKL128_I2CStop
000302  2000              MOVS     r0,#0                 ;345
000304  e7f2              B        |L1.748|
                  |L1.774|
000306  f006001f          AND      r0,r6,#0x1f           ;347
00030a  f7fffffe          BL       VKL128_I2CWRCmd
00030e  f7fffffe          BL       VKL128_I2CSlaveAck
000312  2801              CMP      r0,#1                 ;348
000314  d103              BNE      |L1.798|
000316  f7fffffe          BL       VKL128_I2CStop
00031a  2000              MOVS     r0,#0                 ;351
00031c  e7e6              B        |L1.748|
                  |L1.798|
00031e  f7fffffe          BL       VKL128_I2CStop
000322  f7fffffe          BL       VKL128_I2CStart
000326  207d              MOVS     r0,#0x7d              ;358
000328  f7fffffe          BL       VKL128_I2CWRCmd
00032c  f7fffffe          BL       VKL128_I2CSlaveAck
000330  2801              CMP      r0,#1                 ;359
000332  d103              BNE      |L1.828|
000334  f7fffffe          BL       VKL128_I2CStop
000338  2000              MOVS     r0,#0                 ;362
00033a  e7d7              B        |L1.748|
                  |L1.828|
00033c  2500              MOVS     r5,#0                 ;365
00033e  e007              B        |L1.848|
                  |L1.832|
000340  f7fffffe          BL       VKL128_I2CRDDat
000344  f8040b01          STRB     r0,[r4],#1            ;367
000348  f7fffffe          BL       VKL128_I2CSendAck
00034c  1c68              ADDS     r0,r5,#1              ;365
00034e  b2c5              UXTB     r5,r0                 ;365
                  |L1.848|
000350  1e78              SUBS     r0,r7,#1              ;365
000352  42a8              CMP      r0,r5                 ;365
000354  dcf4              BGT      |L1.832|
000356  f7fffffe          BL       VKL128_I2CRDDat
00035a  f8040b01          STRB     r0,[r4],#1            ;370
00035e  f7fffffe          BL       VKL128_I2CSendNAck
000362  f7fffffe          BL       VKL128_I2CStop
000366  2000              MOVS     r0,#0                 ;374
000368  e7c0              B        |L1.748|
;;;376    /*******************************************************************************
                          ENDP

                  VKL128_DisAll PROC
;;;383    *******************************************************************************/
;;;384    void VKL128_DisAll(unsigned char dat)
00036a  b570              PUSH     {r4-r6,lr}
;;;385    {
00036c  4605              MOV      r5,r0
;;;386    	unsigned char segi;
;;;387    	
;;;388    	for(segi=0;segi<16;segi++)
00036e  2400              MOVS     r4,#0
000370  e003              B        |L1.890|
                  |L1.882|
;;;389    	{
;;;390    		VKL128_dispram[segi]=dat;
000372  4832              LDR      r0,|L1.1084|
000374  5505              STRB     r5,[r0,r4]
000376  1c60              ADDS     r0,r4,#1              ;388
000378  b2c4              UXTB     r4,r0                 ;388
                  |L1.890|
00037a  2c10              CMP      r4,#0x10              ;388
00037c  dbf9              BLT      |L1.882|
;;;391    	}
;;;392    	WritenDataVKL128(0,VKL128_dispram,16);	//8bitݶӦ2SEGÿ4bitݵַ1ÿ8λ1ACK
00037e  2210              MOVS     r2,#0x10
000380  492e              LDR      r1,|L1.1084|
000382  2000              MOVS     r0,#0
000384  f7fffffe          BL       WritenDataVKL128
;;;393    }
000388  bd70              POP      {r4-r6,pc}
;;;394    /*******************************************************************************
                          ENDP

                  VKL128_DisDotOn PROC
;;;401    *******************************************************************************/
;;;402    void VKL128_DisDotOn(unsigned char seg,unsigned char com)
00038a  b5f8              PUSH     {r3-r7,lr}
;;;403    {
00038c  4604              MOV      r4,r0
00038e  460d              MOV      r5,r1
;;;404    	unsigned char addrbyte,addrbit,tempdat;
;;;405    	
;;;406    	//com/segӦʾRAMַbit
;;;407    	addrbyte=seg/2*2;
000390  4620              MOV      r0,r4
000392  eb0471d0          ADD      r1,r4,r0,LSR #31
000396  1049              ASRS     r1,r1,#1
000398  0649              LSLS     r1,r1,#25
00039a  0e0f              LSRS     r7,r1,#24
;;;408    	if((seg%2)==0)
00039c  eb0471d0          ADD      r1,r4,r0,LSR #31
0003a0  1049              ASRS     r1,r1,#1
0003a2  eba40141          SUB      r1,r4,r1,LSL #1
0003a6  b919              CBNZ     r1,|L1.944|
;;;409    		addrbit=(1<<com);
0003a8  2001              MOVS     r0,#1
0003aa  40a8              LSLS     r0,r0,r5
0003ac  b2c6              UXTB     r6,r0
0003ae  e003              B        |L1.952|
                  |L1.944|
;;;410    	else
;;;411    		addrbit=(1<<(4+com));
0003b0  1d28              ADDS     r0,r5,#4
0003b2  2101              MOVS     r1,#1
0003b4  4081              LSLS     r1,r1,r0
0003b6  b2ce              UXTB     r6,r1
                  |L1.952|
;;;412    	tempdat=VKL128_dispram[seg/2]|addrbit;
0003b8  4620              MOV      r0,r4
0003ba  eb0471d0          ADD      r1,r4,r0,LSR #31
0003be  1049              ASRS     r1,r1,#1
0003c0  4a1e              LDR      r2,|L1.1084|
0003c2  5c51              LDRB     r1,[r2,r1]
0003c4  4331              ORRS     r1,r1,r6
0003c6  9100              STR      r1,[sp,#0]
;;;413    	VKL128_dispram[seg/2]=tempdat;
0003c8  f89d1000          LDRB     r1,[sp,#0]
0003cc  eb0472d0          ADD      r2,r4,r0,LSR #31
0003d0  1052              ASRS     r2,r2,#1
0003d2  4b1a              LDR      r3,|L1.1084|
0003d4  5499              STRB     r1,[r3,r2]
;;;414    	WritenDataVKL128(addrbyte,&tempdat,1);		//8bitݶӦ2SEGseg/comӦbit17bitı
0003d6  2201              MOVS     r2,#1
0003d8  4669              MOV      r1,sp
0003da  4638              MOV      r0,r7
0003dc  f7fffffe          BL       WritenDataVKL128
;;;415    }
0003e0  bdf8              POP      {r3-r7,pc}
;;;416    /*******************************************************************************
                          ENDP

                  VKL128_DisDotOff PROC
;;;423    *******************************************************************************/
;;;424    void VKL128_DisDotOff(unsigned char seg,unsigned char com)
0003e2  b5f8              PUSH     {r3-r7,lr}
;;;425    {
0003e4  4604              MOV      r4,r0
0003e6  460d              MOV      r5,r1
;;;426    	unsigned char addrbyte,addrbit,tempdat;
;;;427    	
;;;428    	//com/segӦʾRAMַbit
;;;429    	addrbyte=seg/2*2;
0003e8  4620              MOV      r0,r4
0003ea  eb0471d0          ADD      r1,r4,r0,LSR #31
0003ee  1049              ASRS     r1,r1,#1
0003f0  0649              LSLS     r1,r1,#25
0003f2  0e0f              LSRS     r7,r1,#24
;;;430    	if((seg%2)==0)
0003f4  eb0471d0          ADD      r1,r4,r0,LSR #31
0003f8  1049              ASRS     r1,r1,#1
0003fa  eba40141          SUB      r1,r4,r1,LSL #1
0003fe  b919              CBNZ     r1,|L1.1032|
;;;431    		addrbit=(1<<com);
000400  2001              MOVS     r0,#1
000402  40a8              LSLS     r0,r0,r5
000404  b2c6              UXTB     r6,r0
000406  e003              B        |L1.1040|
                  |L1.1032|
;;;432    	else
;;;433    		addrbit=(1<<(4+com));
000408  1d28              ADDS     r0,r5,#4
00040a  2101              MOVS     r1,#1
00040c  4081              LSLS     r1,r1,r0
00040e  b2ce              UXTB     r6,r1
                  |L1.1040|
;;;434    	tempdat=VKL128_dispram[seg/2]&(~addrbit);
000410  4620              MOV      r0,r4
000412  eb0471d0          ADD      r1,r4,r0,LSR #31
000416  1049              ASRS     r1,r1,#1
000418  4a08              LDR      r2,|L1.1084|
00041a  5c51              LDRB     r1,[r2,r1]
00041c  43b1              BICS     r1,r1,r6
00041e  9100              STR      r1,[sp,#0]
;;;435    	VKL128_dispram[seg/2]=tempdat;
000420  f89d1000          LDRB     r1,[sp,#0]
000424  eb0472d0          ADD      r2,r4,r0,LSR #31
000428  1052              ASRS     r2,r2,#1
00042a  4b04              LDR      r3,|L1.1084|
00042c  5499              STRB     r1,[r3,r2]
;;;436    	WritenDataVKL128(addrbyte,&tempdat,1);		//8bitݶӦ2SEGseg/comӦbit07bitı
00042e  2201              MOVS     r2,#1
000430  4669              MOV      r1,sp
000432  e005              B        |L1.1088|
                  |L1.1076|
                          DCD      0x4000487c
                  |L1.1080|
                          DCD      0x40004040
                  |L1.1084|
                          DCD      VKL128_dispram
                  |L1.1088|
000440  4638              MOV      r0,r7
000442  f7fffffe          BL       WritenDataVKL128
;;;437    }
000446  bdf8              POP      {r3-r7,pc}
;;;438    /*******************************************************************************
                          ENDP

                  VKL128_Enter_PowerOff PROC
;;;444    *******************************************************************************/
;;;445    unsigned char VKL128_Enter_PowerOff(void)
000448  b510              PUSH     {r4,lr}
;;;446    {		
;;;447    	VKL128_I2CStart();
00044a  f7fffffe          BL       VKL128_I2CStart
;;;448    	VKL128_I2CWRCmd(VKL128_ADDRWR); 
00044e  207c              MOVS     r0,#0x7c
000450  f7fffffe          BL       VKL128_I2CWRCmd
;;;449    	if( 1 == VKL128_I2CSlaveAck() )
000454  f7fffffe          BL       VKL128_I2CSlaveAck
000458  2801              CMP      r0,#1
00045a  d103              BNE      |L1.1124|
;;;450    	{
;;;451    		VKL128_I2CStop();
00045c  f7fffffe          BL       VKL128_I2CStop
;;;452    		return 1; 
000460  2001              MOVS     r0,#1
                  |L1.1122|
;;;453    	}
;;;454    	VKL128_I2CWRCmd(VKL128_LCD_OFF);		//ʾ
;;;455    	if( 1 == VKL128_I2CSlaveAck() )
;;;456    	{
;;;457    		VKL128_I2CStop();
;;;458    		return 1; 
;;;459    	}
;;;460    	VKL128_I2CStop();
;;;461      return 0; 
;;;462    }
000462  bd10              POP      {r4,pc}
                  |L1.1124|
000464  20c0              MOVS     r0,#0xc0              ;454
000466  f7fffffe          BL       VKL128_I2CWRCmd
00046a  f7fffffe          BL       VKL128_I2CSlaveAck
00046e  2801              CMP      r0,#1                 ;455
000470  d103              BNE      |L1.1146|
000472  f7fffffe          BL       VKL128_I2CStop
000476  2001              MOVS     r0,#1                 ;458
000478  e7f3              B        |L1.1122|
                  |L1.1146|
00047a  f7fffffe          BL       VKL128_I2CStop
00047e  2000              MOVS     r0,#0                 ;461
000480  e7ef              B        |L1.1122|
;;;463    /*******************************************************************************
                          ENDP

                  VKL128_InitSequence PROC
;;;485    *******************************************************************************/
;;;486    unsigned char VKL128_InitSequence(void)
000482  b510              PUSH     {r4,lr}
;;;487    {			
;;;488      //ϵʼʱ򣨲οֲϵ縴λʱͼͲ	
;;;489    	//ϵ100uSʼ
;;;490      Delay_nuS(100);
000484  2064              MOVS     r0,#0x64
000486  f7fffffe          BL       Delay_nuS
;;;491    	//STOPź
;;;492    	VKL128_I2CStop();
00048a  f7fffffe          BL       VKL128_I2CStop
;;;493    	//STARTź
;;;494    	VKL128_I2CStart();
00048e  f7fffffe          BL       VKL128_I2CStart
;;;495    	//SLAVEַ(0x7C)
;;;496    	VKL128_I2CWRCmd(VKL128_ADDRWR); 
000492  207c              MOVS     r0,#0x7c
000494  f7fffffe          BL       VKL128_I2CWRCmd
;;;497    	if( 1 == VKL128_I2CSlaveAck() )
000498  f7fffffe          BL       VKL128_I2CSlaveAck
00049c  2801              CMP      r0,#1
00049e  d103              BNE      |L1.1192|
;;;498    	{
;;;499    		VKL128_I2CStop();	
0004a0  f7fffffe          BL       VKL128_I2CStop
;;;500    		return 1;
0004a4  2001              MOVS     r0,#1
                  |L1.1190|
;;;501    	}
;;;502    	//ϵͳ(λ)
;;;503    	VKL128_I2CWRCmd(VKL128_SOFTRST);
;;;504    	if( 1 == VKL128_I2CSlaveAck() )
;;;505    	{
;;;506    		VKL128_I2CStop();	
;;;507    		return 1;
;;;508    	}
;;;509    	//ʾ(֡Ƶģʽʽ)ΪʵƷֵο
;;;510    	//VKL128_I2CWRCmd(VKL128_FR80HZ|VKL128_SRNOR|VKL128_LINER);  	//ϵĬ 	VDD=5V:18.2uA  	VDD=3.3V:13uA
;;;511    	VKL128_I2CWRCmd(VKL128_FR53HZ|VKL128_SRPM1|VKL128_FRAMER);  //ʡ 		VDD=5V:9.1uA  VDD=3.3V:6.8uA
;;;512    	//VKL128_I2CWRCmd(VKL128_FR80HZ|VKL128_SRHP|VKL128_LINER);  	// 			VDD=5V:20uA  	VDD=3.3V:15uA 
;;;513    	if( 1 == VKL128_I2CSlaveAck() )
;;;514    	{
;;;515    		VKL128_I2CStop();	
;;;516    		return 1;
;;;517    	}
;;;518      //ģʽ
;;;519    	VKL128_I2CWRCmd(VKL128_BIAS_1_3|VKL128_LCD_ON);		//1/3bias,ʾ 
;;;520    	//VKL128_I2CWRCmd(VKL128_BIAS_1_2|VKL128_LCD_ON);		//1/2bias,ʾ 
;;;521    	if( 1 == VKL128_I2CSlaveAck() )
;;;522    	{
;;;523    		VKL128_I2CStop();	
;;;524    		return 1;
;;;525    	}
;;;526    	//STOPź
;;;527    	VKL128_I2CStop();	
;;;528    		
;;;529      return  0; 
;;;530    }
0004a6  bd10              POP      {r4,pc}
                  |L1.1192|
0004a8  20ea              MOVS     r0,#0xea              ;503
0004aa  f7fffffe          BL       VKL128_I2CWRCmd
0004ae  f7fffffe          BL       VKL128_I2CSlaveAck
0004b2  2801              CMP      r0,#1                 ;504
0004b4  d103              BNE      |L1.1214|
0004b6  f7fffffe          BL       VKL128_I2CStop
0004ba  2001              MOVS     r0,#1                 ;507
0004bc  e7f3              B        |L1.1190|
                  |L1.1214|
0004be  20bc              MOVS     r0,#0xbc              ;511
0004c0  f7fffffe          BL       VKL128_I2CWRCmd
0004c4  f7fffffe          BL       VKL128_I2CSlaveAck
0004c8  2801              CMP      r0,#1                 ;513
0004ca  d103              BNE      |L1.1236|
0004cc  f7fffffe          BL       VKL128_I2CStop
0004d0  2001              MOVS     r0,#1                 ;516
0004d2  e7e8              B        |L1.1190|
                  |L1.1236|
0004d4  20c8              MOVS     r0,#0xc8              ;519
0004d6  f7fffffe          BL       VKL128_I2CWRCmd
0004da  f7fffffe          BL       VKL128_I2CSlaveAck
0004de  2801              CMP      r0,#1                 ;521
0004e0  d103              BNE      |L1.1258|
0004e2  f7fffffe          BL       VKL128_I2CStop
0004e6  2001              MOVS     r0,#1                 ;524
0004e8  e7dd              B        |L1.1190|
                  |L1.1258|
0004ea  f7fffffe          BL       VKL128_I2CStop
0004ee  2000              MOVS     r0,#0                 ;529
0004f0  e7d9              B        |L1.1190|
;;;531    /*******************************************************************************
                          ENDP

                  VKL128_Exit_PowerOff PROC
;;;469    *******************************************************************************/
;;;470    unsigned char VKL128_Exit_PowerOff(void)
0004f2  b510              PUSH     {r4,lr}
;;;471    {	
;;;472    	unsigned char errorflag; 
;;;473    	
;;;474    	//˳ģʽ³ʼʱ
;;;475    	errorflag=VKL128_InitSequence();
0004f4  f7fffffe          BL       VKL128_InitSequence
0004f8  4604              MOV      r4,r0
;;;476    	
;;;477      return(errorflag);
0004fa  4620              MOV      r0,r4
;;;478    }
0004fc  bd10              POP      {r4,pc}
;;;479    /*******************************************************************************
                          ENDP

                  VKL128_Lowlevel_Init PROC
;;;537    *******************************************************************************/
;;;538    void VKL128_Lowlevel_Init(void)
0004fe  b510              PUSH     {r4,lr}
;;;539    {
;;;540    	//ͨߵƽͬӵƽת·
;;;541    	//˺ݿͻƬӦ޸	
;;;542    	GPIO_SetMode(VKL128_SCL_PORT, VKL128_SCL_PIN, GPIO_MODE_OUTPUT);
000500  2201              MOVS     r2,#1
000502  03d1              LSLS     r1,r2,#15
000504  4864              LDR      r0,|L1.1688|
000506  f7fffffe          BL       GPIO_SetMode
;;;543    	VKL128_SET_SDA_OUT();
00050a  2201              MOVS     r2,#1
00050c  2120              MOVS     r1,#0x20
00050e  4862              LDR      r0,|L1.1688|
000510  f7fffffe          BL       GPIO_SetMode
;;;544    	
;;;545      //I2C߿Ϊߵƽ	
;;;546    	VKL128_SCL_H();  
000514  2001              MOVS     r0,#1
000516  4961              LDR      r1,|L1.1692|
000518  6008              STR      r0,[r1,#0]
;;;547    	VKL128_SDA_H(); 	
00051a  4960              LDR      r1,|L1.1692|
00051c  3928              SUBS     r1,r1,#0x28
00051e  6008              STR      r0,[r1,#0]
;;;548    }
000520  bd10              POP      {r4,pc}
;;;549    /*******************************************************************************
                          ENDP

                  VKL128_Init PROC
;;;555    *******************************************************************************/
;;;556    void VKL128_Init(void)
000522  b510              PUSH     {r4,lr}
;;;557    {	
;;;558    	//ܽøݿͻƬӦ޸
;;;559    	VKL128_Lowlevel_Init();
000524  f7fffffe          BL       VKL128_Lowlevel_Init
;;;560    	//ʼʱ
;;;561    	VKL128_InitSequence();
000528  f7fffffe          BL       VKL128_InitSequence
;;;562    }
00052c  bd10              POP      {r4,pc}
;;;563    /*******************************************************************************
                          ENDP

                  VKL128_Main PROC
;;;569    *******************************************************************************/
;;;570    void VKL128_Main(void)
00052e  f7fffffe          BL       VKL128_Init
;;;571    {	
;;;572    	VKL128_Init();
;;;573    	
;;;574    	//ѡⲿʱ(OSCI)ƵΪ32KHz(ʵ֡ƵƵ)
;;;575    	//WriteCmdVKL128(VKL128_EXTCLK); //ʾַʱVKL128_ADDRWR5bit0һҪ1
;;;576    	
;;;577    	//˸
;;;578    	//WriteCmdVKL128(VKL128_BLKCTL_05HZ); //˸Ƶ0.5Hz
;;;579    	//WriteCmdVKL128(VKL128_BLKCTL_1HZ); 	//˸Ƶ1Hz
;;;580    	WriteCmdVKL128(VKL128_BLKCTL_2HZ); 	//˸Ƶ2Hz
000532  20f3              MOVS     r0,#0xf3
000534  f7fffffe          BL       WriteCmdVKL128
;;;581    	//WriteCmdVKL128(VKL128_BLKCTL_OFF);	//˸ر
;;;582    	
;;;583    	//ȫǿƿ
;;;584    	WriteCmdVKL128(VKL128_APCTL_ALLON2);	
000538  20fe              MOVS     r0,#0xfe
00053a  f7fffffe          BL       WriteCmdVKL128
;;;585    	Delay_nmS(3000);					//ʱ
00053e  f64030b8          MOV      r0,#0xbb8
000542  f7fffffe          BL       Delay_nmS
;;;586    	//ȫǿƹ
;;;587    	WriteCmdVKL128(VKL128_APCTL_ALLOFF1);
000546  20fd              MOVS     r0,#0xfd
000548  f7fffffe          BL       WriteCmdVKL128
;;;588    	Delay_nmS(1000);					//ʱ
00054c  f44f707a          MOV      r0,#0x3e8
000550  f7fffffe          BL       Delay_nmS
;;;589    	
;;;590    	//ȫǿȡ,ָ
;;;591    	WriteCmdVKL128(VKL128_APCTL_NORMAL);
000554  20fc              MOVS     r0,#0xfc
000556  f7fffffe          BL       WriteCmdVKL128
;;;592    	WriteCmdVKL128(VKL128_BLKCTL_OFF);	//˸ر
00055a  20f0              MOVS     r0,#0xf0
00055c  f7fffffe          BL       WriteCmdVKL128
;;;593    	
;;;594    	VKL128_DisAll(0x00);
000560  2000              MOVS     r0,#0
000562  f7fffffe          BL       VKL128_DisAll
;;;595    	while(1)
000566  e096              B        |L1.1686|
                  |L1.1384|
;;;596    	{		
;;;597    		//LCDȫ
;;;598    		VKL128_DisAll(0xFF);			
000568  20ff              MOVS     r0,#0xff
00056a  f7fffffe          BL       VKL128_DisAll
;;;599    		Delay_nmS(3000);					//ʱ
00056e  f64030b8          MOV      r0,#0xbb8
000572  f7fffffe          BL       Delay_nmS
;;;600    		
;;;601    		//LCDȫ
;;;602    		VKL128_DisAll(0x00);			
000576  2000              MOVS     r0,#0
000578  f7fffffe          BL       VKL128_DisAll
;;;603    		Delay_nmS(3000);					//ʱ
00057c  f64030b8          MOV      r0,#0xbb8
000580  f7fffffe          BL       Delay_nmS
;;;604    	
;;;605    		//LCD
;;;606    		VKL128_DisAll(0x55);			
000584  2055              MOVS     r0,#0x55
000586  f7fffffe          BL       VKL128_DisAll
;;;607    		ReadnDataVKL128(0,VKL128_readbuf,16);	//RAM
00058a  2210              MOVS     r2,#0x10
00058c  4944              LDR      r1,|L1.1696|
00058e  2000              MOVS     r0,#0
000590  f7fffffe          BL       ReadnDataVKL128
;;;608    		Delay_nmS(1500);					//ʱ
000594  f24050dc          MOV      r0,#0x5dc
000598  f7fffffe          BL       Delay_nmS
;;;609    		VKL128_DisAll(0xAA);			
00059c  20aa              MOVS     r0,#0xaa
00059e  f7fffffe          BL       VKL128_DisAll
;;;610    		ReadnDataVKL128(0,VKL128_readbuf,16);	//RAM
0005a2  2210              MOVS     r2,#0x10
0005a4  493e              LDR      r1,|L1.1696|
0005a6  2000              MOVS     r0,#0
0005a8  f7fffffe          BL       ReadnDataVKL128
;;;611    		Delay_nmS(1500);					//ʱ
0005ac  f24050dc          MOV      r0,#0x5dc
0005b0  f7fffffe          BL       Delay_nmS
;;;612    		
;;;613    		//
;;;614    		VKL128_DisAll(0x00);			//LCDȫ		
0005b4  2000              MOVS     r0,#0
0005b6  f7fffffe          BL       VKL128_DisAll
;;;615    		VKL128_Enter_PowerOff();	//ģʽ
0005ba  f7fffffe          BL       VKL128_Enter_PowerOff
;;;616    		Delay_nmS(5000);					//ʱ5S		
0005be  f2413088          MOV      r0,#0x1388
0005c2  f7fffffe          BL       Delay_nmS
;;;617    		VKL128_Exit_PowerOff();	//˳ģʽ
0005c6  f7fffffe          BL       VKL128_Exit_PowerOff
;;;618    				
;;;619    		//LCD
;;;620    		VKL128_DisAll(0x00);			//LCDȫ
0005ca  2000              MOVS     r0,#0
0005cc  f7fffffe          BL       VKL128_DisAll
;;;621    		Delay_nmS(500);						//ʱ
0005d0  f44f70fa          MOV      r0,#0x1f4
0005d4  f7fffffe          BL       Delay_nmS
;;;622    		for(VKL128_segi=0;VKL128_segi<32;VKL128_segi++)//seg0-31
0005d8  2000              MOVS     r0,#0
0005da  4932              LDR      r1,|L1.1700|
0005dc  7008              STRB     r0,[r1,#0]
0005de  e021              B        |L1.1572|
                  |L1.1504|
;;;623    		{
;;;624    			for(VKL128_comi=0;VKL128_comi<4;VKL128_comi++)//com0-3
0005e0  2000              MOVS     r0,#0
0005e2  4931              LDR      r1,|L1.1704|
0005e4  7008              STRB     r0,[r1,#0]
0005e6  e014              B        |L1.1554|
                  |L1.1512|
;;;625    			{
;;;626    				VKL128_DisDotOn(VKL128_segi,VKL128_comi);		//LCD
0005e8  482f              LDR      r0,|L1.1704|
0005ea  7801              LDRB     r1,[r0,#0]  ; VKL128_comi
0005ec  482d              LDR      r0,|L1.1700|
0005ee  7800              LDRB     r0,[r0,#0]  ; VKL128_segi
0005f0  f7fffffe          BL       VKL128_DisDotOn
;;;627    				Delay_nmS(300);				//ʱ
0005f4  f44f7096          MOV      r0,#0x12c
0005f8  f7fffffe          BL       Delay_nmS
;;;628    				VKL128_DisDotOff(VKL128_segi,VKL128_comi);		//ϵʵֵδ˳
0005fc  482a              LDR      r0,|L1.1704|
0005fe  7801              LDRB     r1,[r0,#0]  ; VKL128_comi
000600  4828              LDR      r0,|L1.1700|
000602  7800              LDRB     r0,[r0,#0]  ; VKL128_segi
000604  f7fffffe          BL       VKL128_DisDotOff
000608  4827              LDR      r0,|L1.1704|
00060a  7800              LDRB     r0,[r0,#0]            ;624  ; VKL128_comi
00060c  1c40              ADDS     r0,r0,#1              ;624
00060e  4926              LDR      r1,|L1.1704|
000610  7008              STRB     r0,[r1,#0]            ;624
                  |L1.1554|
000612  4825              LDR      r0,|L1.1704|
000614  7800              LDRB     r0,[r0,#0]            ;624  ; VKL128_comi
000616  2804              CMP      r0,#4                 ;624
000618  dbe6              BLT      |L1.1512|
00061a  4822              LDR      r0,|L1.1700|
00061c  7800              LDRB     r0,[r0,#0]            ;622  ; VKL128_segi
00061e  1c40              ADDS     r0,r0,#1              ;622
000620  4920              LDR      r1,|L1.1700|
000622  7008              STRB     r0,[r1,#0]            ;622
                  |L1.1572|
000624  481f              LDR      r0,|L1.1700|
000626  7800              LDRB     r0,[r0,#0]            ;622  ; VKL128_segi
000628  2820              CMP      r0,#0x20              ;622
00062a  dbd9              BLT      |L1.1504|
;;;629    			}
;;;630    		}
;;;631    		
;;;632    		//LCDر
;;;633    		VKL128_DisAll(0xff);			//LCDȫ
00062c  20ff              MOVS     r0,#0xff
00062e  f7fffffe          BL       VKL128_DisAll
;;;634    		Delay_nmS(500);						//ʱ
000632  f44f70fa          MOV      r0,#0x1f4
000636  f7fffffe          BL       Delay_nmS
;;;635    		for(VKL128_segi=0;VKL128_segi<32;VKL128_segi++)//seg0-31
00063a  2000              MOVS     r0,#0
00063c  4919              LDR      r1,|L1.1700|
00063e  7008              STRB     r0,[r1,#0]
000640  e021              B        |L1.1670|
                  |L1.1602|
;;;636    		{
;;;637    			for(VKL128_comi=0;VKL128_comi<4;VKL128_comi++)//com0-3
000642  2000              MOVS     r0,#0
000644  4918              LDR      r1,|L1.1704|
000646  7008              STRB     r0,[r1,#0]
000648  e014              B        |L1.1652|
                  |L1.1610|
;;;638    			{
;;;639    				VKL128_DisDotOff(VKL128_segi,VKL128_comi);		//LCDر
00064a  4817              LDR      r0,|L1.1704|
00064c  7801              LDRB     r1,[r0,#0]  ; VKL128_comi
00064e  4815              LDR      r0,|L1.1700|
000650  7800              LDRB     r0,[r0,#0]  ; VKL128_segi
000652  f7fffffe          BL       VKL128_DisDotOff
;;;640    				Delay_nmS(300);				//ʱ
000656  f44f7096          MOV      r0,#0x12c
00065a  f7fffffe          BL       Delay_nmS
;;;641    				VKL128_DisDotOn(VKL128_segi,VKL128_comi);		//ϵرպʵֵرգδ˳ر
00065e  4812              LDR      r0,|L1.1704|
000660  7801              LDRB     r1,[r0,#0]  ; VKL128_comi
000662  4810              LDR      r0,|L1.1700|
000664  7800              LDRB     r0,[r0,#0]  ; VKL128_segi
000666  f7fffffe          BL       VKL128_DisDotOn
00066a  480f              LDR      r0,|L1.1704|
00066c  7800              LDRB     r0,[r0,#0]            ;637  ; VKL128_comi
00066e  1c40              ADDS     r0,r0,#1              ;637
000670  490d              LDR      r1,|L1.1704|
000672  7008              STRB     r0,[r1,#0]            ;637
                  |L1.1652|
000674  480c              LDR      r0,|L1.1704|
000676  7800              LDRB     r0,[r0,#0]            ;637  ; VKL128_comi
000678  2804              CMP      r0,#4                 ;637
00067a  dbe6              BLT      |L1.1610|
00067c  4809              LDR      r0,|L1.1700|
00067e  7800              LDRB     r0,[r0,#0]            ;635  ; VKL128_segi
000680  1c40              ADDS     r0,r0,#1              ;635
000682  4908              LDR      r1,|L1.1700|
000684  7008              STRB     r0,[r1,#0]            ;635
                  |L1.1670|
000686  4807              LDR      r0,|L1.1700|
000688  7800              LDRB     r0,[r0,#0]            ;635  ; VKL128_segi
00068a  2820              CMP      r0,#0x20              ;635
00068c  dbd9              BLT      |L1.1602|
;;;642    			}
;;;643    		}		
;;;644    		Delay_nmS(1000);					//ʱ
00068e  f44f707a          MOV      r0,#0x3e8
000692  f7fffffe          BL       Delay_nmS
                  |L1.1686|
000696  e767              B        |L1.1384|
;;;645    	}
;;;646    }
;;;647    /************************END OF FILE****/
                          ENDP

                  |L1.1688|
                          DCD      0x40004040
                  |L1.1692|
                          DCD      0x4000487c
                  |L1.1696|
                          DCD      VKL128_readbuf
                  |L1.1700|
                          DCD      VKL128_segi
                  |L1.1704|
                          DCD      VKL128_comi

                          AREA ||.bss||, DATA, NOINIT, ALIGN=0

                  VKL128_dispram
                          %        16
                  VKL128_readbuf
                          %        16

                          AREA ||.data||, DATA, ALIGN=0

                  VKL128_segi
000000  00                DCB      0x00
                  VKL128_comi
000001  00                DCB      0x00

;*** Start embedded assembler ***

#line 1 "..\\lcd_driver\\VKL128_IO_I2C_DIR.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___19_VKL128_IO_I2C_DIR_c_f70de489____REV16|
#line 114 "..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___19_VKL128_IO_I2C_DIR_c_f70de489____REV16| PROC
#line 115

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___19_VKL128_IO_I2C_DIR_c_f70de489____REVSH|
#line 128
|__asm___19_VKL128_IO_I2C_DIR_c_f70de489____REVSH| PROC
#line 129

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
