; generated by Component: ARM Compiler 5.05 update 2 (build 169) Tool: ArmCC [4d0f38]
; commandline ArmCC [--list --debug -c --asm --interleave -o.\obj\vkl128_io_i2c_quasi.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\vkl128_io_i2c_quasi.d --cpu=Cortex-M4.fp --apcs=interwork -O0 --diag_suppress=9931 -I..\..\..\Library\CMSIS\Include -I..\..\..\Library\Device\Nuvoton\M451Series\Include -I..\..\..\Library\StdDriver\inc -I..\Bsp -I..\User -I..\lcd_driver -I..\exti_driver -I..\led_driver -I..\touch -I..\dotmatix_lcd -I..\KH -IC:\Users\Administator\Desktop\͹ϵ_VKL\VKL\VKL128_TESTCODE\project\VKL144_FUNC\Keil\RTE -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\4.3.0\CMSIS\Include -D__UVISION_VERSION=515 -D_RTE_ --omf_browse=.\obj\vkl128_io_i2c_quasi.crf ..\lcd_driver\VKL128_IO_I2C_QUASI.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  Delay_nuS PROC
;;;35     *******************************************************************************/
;;;36     void Delay_nuS(unsigned int n)	   
000000  e007              B        |L1.18|
                  |L1.2|
;;;37     {
;;;38     	unsigned char i;
;;;39     	while(n--)
;;;40     	{
;;;41     		i=10;
000002  210a              MOVS     r1,#0xa
;;;42     		while(i--)
000004  e000              B        |L1.8|
                  |L1.6|
;;;43     		{//nopָݵƬӦ޸
;;;44     			__nop();
000006  bf00              NOP      
                  |L1.8|
000008  000a              MOVS     r2,r1                 ;42
00000a  f1a10301          SUB      r3,r1,#1              ;42
00000e  b2d9              UXTB     r1,r3                 ;42
000010  d1f9              BNE      |L1.6|
                  |L1.18|
000012  0002              MOVS     r2,r0                 ;39
000014  f1a00001          SUB      r0,r0,#1              ;39
000018  d1f3              BNE      |L1.2|
;;;45     		}
;;;46     	}
;;;47     }
00001a  4770              BX       lr
;;;48     /*******************************************************************************
                          ENDP

                  Delay_nmS PROC
;;;54     *******************************************************************************/
;;;55     void Delay_nmS(unsigned long int n)
00001c  b510              PUSH     {r4,lr}
;;;56     {
00001e  4604              MOV      r4,r0
;;;57     	while(n--)
000020  e003              B        |L1.42|
                  |L1.34|
;;;58     	{
;;;59     		Delay_nuS(1000);
000022  f44f707a          MOV      r0,#0x3e8
000026  f7fffffe          BL       Delay_nuS
                  |L1.42|
00002a  0020              MOVS     r0,r4                 ;57
00002c  f1a40401          SUB      r4,r4,#1              ;57
000030  d1f7              BNE      |L1.34|
;;;60     	}
;;;61     }
000032  bd10              POP      {r4,pc}
;;;62     /*******************************************************************************
                          ENDP

                  VKL128_I2CStart PROC
;;;68     *******************************************************************************/
;;;69     void VKL128_I2CStart( void )
000034  b500              PUSH     {lr}
;;;70     {
;;;71       VKL128_SCL_H();
000036  2001              MOVS     r0,#1
000038  49f7              LDR      r1,|L1.1048|
00003a  6008              STR      r0,[r1,#0]
;;;72       VKL128_SDA_H();
00003c  49f6              LDR      r1,|L1.1048|
00003e  3928              SUBS     r1,r1,#0x28
000040  6008              STR      r0,[r1,#0]
;;;73       Delay_nuS(VKL128_CLK);
000042  2005              MOVS     r0,#5
000044  f7fffffe          BL       Delay_nuS
;;;74       VKL128_SDA_L();
000048  2000              MOVS     r0,#0
00004a  49f3              LDR      r1,|L1.1048|
00004c  3928              SUBS     r1,r1,#0x28
00004e  6008              STR      r0,[r1,#0]
;;;75       Delay_nuS(VKL128_CLK);
000050  2005              MOVS     r0,#5
000052  f7fffffe          BL       Delay_nuS
;;;76     }
000056  bd00              POP      {pc}
;;;77     /*******************************************************************************
                          ENDP

                  VKL128_I2CStop PROC
;;;83     *******************************************************************************/
;;;84     void VKL128_I2CStop( void )
000058  b500              PUSH     {lr}
;;;85     {
;;;86       VKL128_SCL_H();
00005a  2001              MOVS     r0,#1
00005c  49ee              LDR      r1,|L1.1048|
00005e  6008              STR      r0,[r1,#0]
;;;87       VKL128_SDA_L();
000060  2000              MOVS     r0,#0
000062  49ed              LDR      r1,|L1.1048|
000064  3928              SUBS     r1,r1,#0x28
000066  6008              STR      r0,[r1,#0]
;;;88       Delay_nuS(VKL128_CLK);
000068  2005              MOVS     r0,#5
00006a  f7fffffe          BL       Delay_nuS
;;;89       VKL128_SDA_H();
00006e  2001              MOVS     r0,#1
000070  49e9              LDR      r1,|L1.1048|
000072  3928              SUBS     r1,r1,#0x28
000074  6008              STR      r0,[r1,#0]
;;;90       Delay_nuS(VKL128_CLK);
000076  2005              MOVS     r0,#5
000078  f7fffffe          BL       Delay_nuS
;;;91     }
00007c  bd00              POP      {pc}
;;;92     /*******************************************************************************
                          ENDP

                  VKL128_I2CSlaveAck PROC
;;;98     *******************************************************************************/
;;;99     unsigned char VKL128_I2CSlaveAck( void )
00007e  b530              PUSH     {r4,r5,lr}
;;;100    {
;;;101      unsigned int TimeOut;
;;;102      unsigned char RetValue;
;;;103    	
;;;104      VKL128_SCL_L();
000080  2000              MOVS     r0,#0
000082  49e5              LDR      r1,|L1.1048|
000084  6008              STR      r0,[r1,#0]
;;;105      Delay_nuS(VKL128_CLK);
000086  2005              MOVS     r0,#5
000088  f7fffffe          BL       Delay_nuS
;;;106      VKL128_SCL_H();//9SCLʱ
00008c  2001              MOVS     r0,#1
00008e  49e2              LDR      r1,|L1.1048|
000090  6008              STR      r0,[r1,#0]
;;;107      TimeOut = 10000;
000092  f2427510          MOV      r5,#0x2710
;;;108      while( TimeOut-- > 0 )
000096  e007              B        |L1.168|
                  |L1.152|
;;;109      {
;;;110        if( VKL128_GET_SDA()!=0 )//ȡack
000098  48df              LDR      r0,|L1.1048|
00009a  3828              SUBS     r0,r0,#0x28
00009c  6800              LDR      r0,[r0,#0]
00009e  b108              CBZ      r0,|L1.164|
;;;111        {
;;;112          RetValue = 1;
0000a0  2401              MOVS     r4,#1
0000a2  e001              B        |L1.168|
                  |L1.164|
;;;113        }
;;;114        else
;;;115        {
;;;116          RetValue = 0;
0000a4  2400              MOVS     r4,#0
;;;117          break;
0000a6  e003              B        |L1.176|
                  |L1.168|
0000a8  0028              MOVS     r0,r5                 ;108
0000aa  f1a50501          SUB      r5,r5,#1              ;108
0000ae  d1f3              BNE      |L1.152|
                  |L1.176|
0000b0  bf00              NOP      
;;;118        }
;;;119      } 
;;;120    	VKL128_SCL_L(); //һʱΪ,ݻSTOPźš
0000b2  2000              MOVS     r0,#0
0000b4  49d8              LDR      r1,|L1.1048|
0000b6  6008              STR      r0,[r1,#0]
;;;121      
;;;122      return RetValue;
0000b8  4620              MOV      r0,r4
;;;123    }
0000ba  bd30              POP      {r4,r5,pc}
;;;124    /*******************************************************************************
                          ENDP

                  VKL128_I2CSendAck PROC
;;;130    *******************************************************************************/
;;;131    void VKL128_I2CSendAck( void )
0000bc  b500              PUSH     {lr}
;;;132    {
;;;133      VKL128_SCL_L();
0000be  2000              MOVS     r0,#0
0000c0  49d5              LDR      r1,|L1.1048|
0000c2  6008              STR      r0,[r1,#0]
;;;134      VKL128_SDA_L();
0000c4  49d4              LDR      r1,|L1.1048|
0000c6  3928              SUBS     r1,r1,#0x28
0000c8  6008              STR      r0,[r1,#0]
;;;135      Delay_nuS(VKL128_CLK*2);
0000ca  200a              MOVS     r0,#0xa
0000cc  f7fffffe          BL       Delay_nuS
;;;136      VKL128_SCL_H();
0000d0  2001              MOVS     r0,#1
0000d2  49d1              LDR      r1,|L1.1048|
0000d4  6008              STR      r0,[r1,#0]
;;;137      Delay_nuS(VKL128_CLK*2);
0000d6  200a              MOVS     r0,#0xa
0000d8  f7fffffe          BL       Delay_nuS
;;;138      VKL128_SCL_L();
0000dc  2000              MOVS     r0,#0
0000de  49ce              LDR      r1,|L1.1048|
0000e0  6008              STR      r0,[r1,#0]
;;;139      VKL128_SDA_H();
0000e2  2001              MOVS     r0,#1
0000e4  49cc              LDR      r1,|L1.1048|
0000e6  3928              SUBS     r1,r1,#0x28
0000e8  6008              STR      r0,[r1,#0]
;;;140    }
0000ea  bd00              POP      {pc}
;;;141    /*******************************************************************************
                          ENDP

                  VKL128_I2CSendNAck PROC
;;;147    *******************************************************************************/
;;;148    void VKL128_I2CSendNAck( void )
0000ec  b500              PUSH     {lr}
;;;149    {
;;;150      VKL128_SCL_L();
0000ee  2000              MOVS     r0,#0
0000f0  49c9              LDR      r1,|L1.1048|
0000f2  6008              STR      r0,[r1,#0]
;;;151      VKL128_SDA_H();
0000f4  2001              MOVS     r0,#1
0000f6  49c8              LDR      r1,|L1.1048|
0000f8  3928              SUBS     r1,r1,#0x28
0000fa  6008              STR      r0,[r1,#0]
;;;152      Delay_nuS(VKL128_CLK);
0000fc  2005              MOVS     r0,#5
0000fe  f7fffffe          BL       Delay_nuS
;;;153      VKL128_SCL_H();
000102  2001              MOVS     r0,#1
000104  49c4              LDR      r1,|L1.1048|
000106  6008              STR      r0,[r1,#0]
;;;154      Delay_nuS(VKL128_CLK);
000108  2005              MOVS     r0,#5
00010a  f7fffffe          BL       Delay_nuS
;;;155    }
00010e  bd00              POP      {pc}
;;;156    /*******************************************************************************
                          ENDP

                  VKL128_I2CWRCmd PROC
;;;162    *******************************************************************************/
;;;163    void VKL128_I2CWRCmd( unsigned char cmd )
000110  b530              PUSH     {r4,r5,lr}
;;;164    {
000112  4604              MOV      r4,r0
;;;165    	unsigned char i=8;
000114  2508              MOVS     r5,#8
;;;166    	
;;;167    	while (i--)
000116  e019              B        |L1.332|
                  |L1.280|
;;;168    	{ 
;;;169    		VKL128_SCL_L();
000118  2000              MOVS     r0,#0
00011a  49bf              LDR      r1,|L1.1048|
00011c  6008              STR      r0,[r1,#0]
;;;170    		if(cmd&0x80)
00011e  f0040080          AND      r0,r4,#0x80
000122  b120              CBZ      r0,|L1.302|
;;;171    			VKL128_SDA_H();
000124  2001              MOVS     r0,#1
000126  49bc              LDR      r1,|L1.1048|
000128  3928              SUBS     r1,r1,#0x28
00012a  6008              STR      r0,[r1,#0]
00012c  e003              B        |L1.310|
                  |L1.302|
;;;172    		else
;;;173    			VKL128_SDA_L();
00012e  2000              MOVS     r0,#0
000130  49b9              LDR      r1,|L1.1048|
000132  3928              SUBS     r1,r1,#0x28
000134  6008              STR      r0,[r1,#0]
                  |L1.310|
;;;174    		cmd<<=1; 
000136  0660              LSLS     r0,r4,#25
000138  0e04              LSRS     r4,r0,#24
;;;175    		Delay_nuS(VKL128_CLK);
00013a  2005              MOVS     r0,#5
00013c  f7fffffe          BL       Delay_nuS
;;;176    		VKL128_SCL_H();     
000140  2001              MOVS     r0,#1
000142  49b5              LDR      r1,|L1.1048|
000144  6008              STR      r0,[r1,#0]
;;;177    		Delay_nuS(VKL128_CLK);
000146  2005              MOVS     r0,#5
000148  f7fffffe          BL       Delay_nuS
                  |L1.332|
00014c  0028              MOVS     r0,r5                 ;167
00014e  f1a50101          SUB      r1,r5,#1              ;167
000152  b2cd              UXTB     r5,r1                 ;167
000154  d1e0              BNE      |L1.280|
;;;178    	}
;;;179    }
000156  bd30              POP      {r4,r5,pc}
;;;180    /*******************************************************************************
                          ENDP

                  VKL128_I2CWRDat PROC
;;;186    *******************************************************************************/
;;;187    void VKL128_I2CWRDat( unsigned char dat )
000158  b530              PUSH     {r4,r5,lr}
;;;188    {
00015a  4604              MOV      r4,r0
;;;189    	unsigned char i=8;
00015c  2508              MOVS     r5,#8
;;;190    	while (i--)
00015e  e018              B        |L1.402|
                  |L1.352|
;;;191    	{ 
;;;192    		VKL128_SCL_L();
000160  2000              MOVS     r0,#0
000162  49ad              LDR      r1,|L1.1048|
000164  6008              STR      r0,[r1,#0]
;;;193    		if(dat&0x01)
000166  f0040001          AND      r0,r4,#1
00016a  b120              CBZ      r0,|L1.374|
;;;194    			VKL128_SDA_H();
00016c  2001              MOVS     r0,#1
00016e  49aa              LDR      r1,|L1.1048|
000170  3928              SUBS     r1,r1,#0x28
000172  6008              STR      r0,[r1,#0]
000174  e003              B        |L1.382|
                  |L1.374|
;;;195    		else
;;;196    			VKL128_SDA_L();
000176  2000              MOVS     r0,#0
000178  49a7              LDR      r1,|L1.1048|
00017a  3928              SUBS     r1,r1,#0x28
00017c  6008              STR      r0,[r1,#0]
                  |L1.382|
;;;197    		dat>>=1; 
00017e  1064              ASRS     r4,r4,#1
;;;198    		Delay_nuS(VKL128_CLK);
000180  2005              MOVS     r0,#5
000182  f7fffffe          BL       Delay_nuS
;;;199    		VKL128_SCL_H();     
000186  2001              MOVS     r0,#1
000188  49a3              LDR      r1,|L1.1048|
00018a  6008              STR      r0,[r1,#0]
;;;200    		Delay_nuS(VKL128_CLK);
00018c  2005              MOVS     r0,#5
00018e  f7fffffe          BL       Delay_nuS
                  |L1.402|
000192  0028              MOVS     r0,r5                 ;190
000194  f1a50101          SUB      r1,r5,#1              ;190
000198  b2cd              UXTB     r5,r1                 ;190
00019a  d1e1              BNE      |L1.352|
;;;201    	}
;;;202    }
00019c  bd30              POP      {r4,r5,pc}
;;;203    
                          ENDP

                  VKL128_I2CRDDat PROC
;;;210    *******************************************************************************/
;;;211    unsigned char VKL128_I2CRDDat( void )
00019e  b530              PUSH     {r4,r5,lr}
;;;212    {
;;;213    	unsigned char i,RetValue;
;;;214    	
;;;215    	RetValue=0;	
0001a0  2400              MOVS     r4,#0
;;;216      for( i=0; i<8; i++ )
0001a2  2500              MOVS     r5,#0
0001a4  e014              B        |L1.464|
                  |L1.422|
;;;217      {
;;;218    		RetValue>>=1; 
0001a6  1064              ASRS     r4,r4,#1
;;;219    		VKL128_SCL_L();     
0001a8  2000              MOVS     r0,#0
0001aa  499b              LDR      r1,|L1.1048|
0001ac  6008              STR      r0,[r1,#0]
;;;220    		Delay_nuS(VKL128_CLK);
0001ae  2005              MOVS     r0,#5
0001b0  f7fffffe          BL       Delay_nuS
;;;221    		VKL128_SCL_H();
0001b4  2001              MOVS     r0,#1
0001b6  4998              LDR      r1,|L1.1048|
0001b8  6008              STR      r0,[r1,#0]
;;;222    		Delay_nuS(VKL128_CLK);
0001ba  2005              MOVS     r0,#5
0001bc  f7fffffe          BL       Delay_nuS
;;;223    		if( VKL128_GET_SDA()!=0 )
0001c0  4895              LDR      r0,|L1.1048|
0001c2  3828              SUBS     r0,r0,#0x28
0001c4  6800              LDR      r0,[r0,#0]
0001c6  b108              CBZ      r0,|L1.460|
;;;224    			RetValue|=0x80;
0001c8  f0440480          ORR      r4,r4,#0x80
                  |L1.460|
0001cc  1c68              ADDS     r0,r5,#1              ;216
0001ce  b2c5              UXTB     r5,r0                 ;216
                  |L1.464|
0001d0  2d08              CMP      r5,#8                 ;216
0001d2  dbe8              BLT      |L1.422|
;;;225    	}
;;;226      
;;;227      return RetValue;
0001d4  4620              MOV      r0,r4
;;;228    }
0001d6  bd30              POP      {r4,r5,pc}
;;;229    /*******************************************************************************
                          ENDP

                  WriteCmdVKL128 PROC
;;;235    *******************************************************************************/
;;;236    unsigned char  WriteCmdVKL128(unsigned char cmd)
0001d8  b510              PUSH     {r4,lr}
;;;237    {
0001da  4604              MOV      r4,r0
;;;238    	//STARTź	
;;;239    	VKL128_I2CStart(); 									
0001dc  f7fffffe          BL       VKL128_I2CStart
;;;240    	//SLAVEַ
;;;241    	VKL128_I2CWRCmd(VKL128_ADDRWR); 	
0001e0  207c              MOVS     r0,#0x7c
0001e2  f7fffffe          BL       VKL128_I2CWRCmd
;;;242    	if( 1 == VKL128_I2CSlaveAck() )
0001e6  f7fffffe          BL       VKL128_I2CSlaveAck
0001ea  2801              CMP      r0,#1
0001ec  d103              BNE      |L1.502|
;;;243    	{
;;;244    		VKL128_I2CStop();													
0001ee  f7fffffe          BL       VKL128_I2CStop
;;;245    		return 0;										
0001f2  2000              MOVS     r0,#0
                  |L1.500|
;;;246    	}
;;;247    	
;;;248    	VKL128_I2CWRCmd(cmd); 						
;;;249    	if( 1 == VKL128_I2CSlaveAck() )
;;;250    	{
;;;251    		VKL128_I2CStop();													
;;;252    		return 0;
;;;253    	}
;;;254    	//STOPź
;;;255    	 VKL128_I2CStop();											
;;;256    	 return 0;    
;;;257    }
0001f4  bd10              POP      {r4,pc}
                  |L1.502|
0001f6  4620              MOV      r0,r4                 ;248
0001f8  f7fffffe          BL       VKL128_I2CWRCmd
0001fc  f7fffffe          BL       VKL128_I2CSlaveAck
000200  2801              CMP      r0,#1                 ;249
000202  d103              BNE      |L1.524|
000204  f7fffffe          BL       VKL128_I2CStop
000208  2000              MOVS     r0,#0                 ;252
00020a  e7f3              B        |L1.500|
                  |L1.524|
00020c  f7fffffe          BL       VKL128_I2CStop
000210  2000              MOVS     r0,#0                 ;256
000212  e7ef              B        |L1.500|
;;;258    /*******************************************************************************
                          ENDP

                  WritenDataVKL128 PROC
;;;266    *******************************************************************************/
;;;267    unsigned char  WritenDataVKL128(unsigned char Addr,unsigned char *Databuf,unsigned char Cnt)
000214  b5f0              PUSH     {r4-r7,lr}
;;;268    {
000216  4606              MOV      r6,r0
000218  460c              MOV      r4,r1
00021a  4617              MOV      r7,r2
;;;269    	unsigned char n;
;;;270    	
;;;271    	//STARTź	
;;;272    	VKL128_I2CStart(); 									
00021c  f7fffffe          BL       VKL128_I2CStart
;;;273    	//SLAVEַ
;;;274    	VKL128_I2CWRCmd(VKL128_ADDRWR); 	
000220  207c              MOVS     r0,#0x7c
000222  f7fffffe          BL       VKL128_I2CWRCmd
;;;275    	if( 1 == VKL128_I2CSlaveAck() )
000226  f7fffffe          BL       VKL128_I2CSlaveAck
00022a  2801              CMP      r0,#1
00022c  d103              BNE      |L1.566|
;;;276    	{
;;;277    		VKL128_I2CStop();													
00022e  f7fffffe          BL       VKL128_I2CStop
;;;278    		return 0;										
000232  2000              MOVS     r0,#0
                  |L1.564|
;;;279    	}
;;;280    	//ʾRAMʼַ
;;;281    	//ѡڲʱӣOSCIţVKL128_ADDRWR5 bit0һҪ0
;;;282      //ѡⲿʱӣOSCIţVKL128_ADDRWR5 bit0һҪ1                              
;;;283    	VKL128_I2CWRCmd(VKL128_ADDR5_0); 
;;;284    	if( 1 == VKL128_I2CSlaveAck() )
;;;285    	{
;;;286    		VKL128_I2CStop();													
;;;287    		return 0; 
;;;288    	}
;;;289    	VKL128_I2CWRCmd(Addr&0x1f); 						
;;;290    	if( 1 == VKL128_I2CSlaveAck() )
;;;291    	{
;;;292    		VKL128_I2CStop();													
;;;293    		return 0;
;;;294    	}
;;;295    	//CntݵʾRAM
;;;296    	for(n=0;n<Cnt;n++)
;;;297    	{ 
;;;298    		VKL128_I2CWRDat(*Databuf++);
;;;299    		if( VKL128_I2CSlaveAck()==1 )
;;;300    		{
;;;301    			VKL128_I2CStop();													
;;;302    			return 0;
;;;303    		}
;;;304    	}
;;;305    	//STOPź
;;;306    	 VKL128_I2CStop();											
;;;307    	 return 0;    
;;;308    }
000234  bdf0              POP      {r4-r7,pc}
                  |L1.566|
000236  20e8              MOVS     r0,#0xe8              ;283
000238  f7fffffe          BL       VKL128_I2CWRCmd
00023c  f7fffffe          BL       VKL128_I2CSlaveAck
000240  2801              CMP      r0,#1                 ;284
000242  d103              BNE      |L1.588|
000244  f7fffffe          BL       VKL128_I2CStop
000248  2000              MOVS     r0,#0                 ;287
00024a  e7f3              B        |L1.564|
                  |L1.588|
00024c  f006001f          AND      r0,r6,#0x1f           ;289
000250  f7fffffe          BL       VKL128_I2CWRCmd
000254  f7fffffe          BL       VKL128_I2CSlaveAck
000258  2801              CMP      r0,#1                 ;290
00025a  d103              BNE      |L1.612|
00025c  f7fffffe          BL       VKL128_I2CStop
000260  2000              MOVS     r0,#0                 ;293
000262  e7e7              B        |L1.564|
                  |L1.612|
000264  2500              MOVS     r5,#0                 ;296
000266  e00d              B        |L1.644|
                  |L1.616|
000268  f8140b01          LDRB     r0,[r4],#1            ;298
00026c  f7fffffe          BL       VKL128_I2CWRDat
000270  f7fffffe          BL       VKL128_I2CSlaveAck
000274  2801              CMP      r0,#1                 ;299
000276  d103              BNE      |L1.640|
000278  f7fffffe          BL       VKL128_I2CStop
00027c  2000              MOVS     r0,#0                 ;302
00027e  e7d9              B        |L1.564|
                  |L1.640|
000280  1c68              ADDS     r0,r5,#1              ;296
000282  b2c5              UXTB     r5,r0                 ;296
                  |L1.644|
000284  42bd              CMP      r5,r7                 ;296
000286  dbef              BLT      |L1.616|
000288  f7fffffe          BL       VKL128_I2CStop
00028c  2000              MOVS     r0,#0                 ;307
00028e  e7d1              B        |L1.564|
;;;309    
                          ENDP

                  ReadnDataVKL128 PROC
;;;318    *******************************************************************************/
;;;319    unsigned char  ReadnDataVKL128(unsigned char Addr,unsigned char *Databuf,unsigned char Cnt)
000290  b5f0              PUSH     {r4-r7,lr}
;;;320    {
000292  4606              MOV      r6,r0
000294  460c              MOV      r4,r1
000296  4617              MOV      r7,r2
;;;321    	unsigned char n;
;;;322    	
;;;323    	//STARTź	
;;;324    	VKL128_I2CStart(); 									
000298  f7fffffe          BL       VKL128_I2CStart
;;;325    	//SLAVEַд
;;;326    	VKL128_I2CWRCmd(VKL128_ADDRWR); 	
00029c  207c              MOVS     r0,#0x7c
00029e  f7fffffe          BL       VKL128_I2CWRCmd
;;;327    	if( 1 == VKL128_I2CSlaveAck() )
0002a2  f7fffffe          BL       VKL128_I2CSlaveAck
0002a6  2801              CMP      r0,#1
0002a8  d103              BNE      |L1.690|
;;;328    	{
;;;329    		VKL128_I2CStop();													
0002aa  f7fffffe          BL       VKL128_I2CStop
;;;330    		return 0;										
0002ae  2000              MOVS     r0,#0
                  |L1.688|
;;;331    	}
;;;332    	//ʾRAMʼַ
;;;333    	//ѡڲʱӣOSCIţVKL128_ADDRWR5 bit0һҪ0
;;;334      //ѡⲿʱӣOSCIţVKL128_ADDRWR5 bit0һҪ1                              
;;;335    	VKL128_I2CWRCmd(VKL128_ADDR5_0); 
;;;336    	if( 1 == VKL128_I2CSlaveAck() )
;;;337    	{
;;;338    		VKL128_I2CStop();													
;;;339    		return 0; 
;;;340    	}
;;;341    	VKL128_I2CWRCmd(Addr&0x1f); 						
;;;342    	if( 1 == VKL128_I2CSlaveAck() )
;;;343    	{
;;;344    		VKL128_I2CStop();													
;;;345    		return 0;
;;;346    	}
;;;347    	//STOPź
;;;348    	 VKL128_I2CStop();	
;;;349    	//STARTź	
;;;350    	VKL128_I2CStart(); 									
;;;351    	//SLAVEַ
;;;352    	VKL128_I2CWRCmd(VKL128_ADDRRD); 	
;;;353    	if( 1 == VKL128_I2CSlaveAck() )
;;;354    	{
;;;355    		VKL128_I2CStop();													
;;;356    		return 0;										
;;;357    	}	
;;;358    	//CntݵʾRAM
;;;359    	for(n=0;n<Cnt-1;n++)
;;;360    	{ 
;;;361    		*Databuf++=VKL128_I2CRDDat();
;;;362    		VKL128_I2CSendAck();
;;;363    	}
;;;364    	*Databuf++=VKL128_I2CRDDat();
;;;365    	VKL128_I2CSendNAck();
;;;366    	//STOPź
;;;367    	 VKL128_I2CStop();											
;;;368    	 return 0;    
;;;369    }
0002b0  bdf0              POP      {r4-r7,pc}
                  |L1.690|
0002b2  20e8              MOVS     r0,#0xe8              ;335
0002b4  f7fffffe          BL       VKL128_I2CWRCmd
0002b8  f7fffffe          BL       VKL128_I2CSlaveAck
0002bc  2801              CMP      r0,#1                 ;336
0002be  d103              BNE      |L1.712|
0002c0  f7fffffe          BL       VKL128_I2CStop
0002c4  2000              MOVS     r0,#0                 ;339
0002c6  e7f3              B        |L1.688|
                  |L1.712|
0002c8  f006001f          AND      r0,r6,#0x1f           ;341
0002cc  f7fffffe          BL       VKL128_I2CWRCmd
0002d0  f7fffffe          BL       VKL128_I2CSlaveAck
0002d4  2801              CMP      r0,#1                 ;342
0002d6  d103              BNE      |L1.736|
0002d8  f7fffffe          BL       VKL128_I2CStop
0002dc  2000              MOVS     r0,#0                 ;345
0002de  e7e7              B        |L1.688|
                  |L1.736|
0002e0  f7fffffe          BL       VKL128_I2CStop
0002e4  f7fffffe          BL       VKL128_I2CStart
0002e8  207d              MOVS     r0,#0x7d              ;352
0002ea  f7fffffe          BL       VKL128_I2CWRCmd
0002ee  f7fffffe          BL       VKL128_I2CSlaveAck
0002f2  2801              CMP      r0,#1                 ;353
0002f4  d103              BNE      |L1.766|
0002f6  f7fffffe          BL       VKL128_I2CStop
0002fa  2000              MOVS     r0,#0                 ;356
0002fc  e7d8              B        |L1.688|
                  |L1.766|
0002fe  2500              MOVS     r5,#0                 ;359
000300  e007              B        |L1.786|
                  |L1.770|
000302  f7fffffe          BL       VKL128_I2CRDDat
000306  f8040b01          STRB     r0,[r4],#1            ;361
00030a  f7fffffe          BL       VKL128_I2CSendAck
00030e  1c68              ADDS     r0,r5,#1              ;359
000310  b2c5              UXTB     r5,r0                 ;359
                  |L1.786|
000312  1e78              SUBS     r0,r7,#1              ;359
000314  42a8              CMP      r0,r5                 ;359
000316  dcf4              BGT      |L1.770|
000318  f7fffffe          BL       VKL128_I2CRDDat
00031c  f8040b01          STRB     r0,[r4],#1            ;364
000320  f7fffffe          BL       VKL128_I2CSendNAck
000324  f7fffffe          BL       VKL128_I2CStop
000328  2000              MOVS     r0,#0                 ;368
00032a  e7c1              B        |L1.688|
;;;370    /*******************************************************************************
                          ENDP

                  VKL128_DisAll PROC
;;;377    *******************************************************************************/
;;;378    void VKL128_DisAll(unsigned char dat)
00032c  b530              PUSH     {r4,r5,lr}
;;;379    {
00032e  4605              MOV      r5,r0
;;;380    	unsigned char segi;
;;;381    	
;;;382    	for(segi=0;segi<16;segi++)
000330  2400              MOVS     r4,#0
000332  e003              B        |L1.828|
                  |L1.820|
;;;383    	{
;;;384    		VKL128_dispram[segi]=dat;
000334  4839              LDR      r0,|L1.1052|
000336  5505              STRB     r5,[r0,r4]
000338  1c60              ADDS     r0,r4,#1              ;382
00033a  b2c4              UXTB     r4,r0                 ;382
                  |L1.828|
00033c  2c10              CMP      r4,#0x10              ;382
00033e  dbf9              BLT      |L1.820|
;;;385    	}
;;;386    	WritenDataVKL128(0,VKL128_dispram,16);	//8bitݶӦ2SEGÿ4bitݵַ1ÿ8λ1ACK
000340  2210              MOVS     r2,#0x10
000342  4936              LDR      r1,|L1.1052|
000344  2000              MOVS     r0,#0
000346  f7fffffe          BL       WritenDataVKL128
;;;387    }
00034a  bd30              POP      {r4,r5,pc}
;;;388    /*******************************************************************************
                          ENDP

                  VKL128_DisDotOn PROC
;;;395    *******************************************************************************/
;;;396    void VKL128_DisDotOn(unsigned char seg,unsigned char com)
00034c  b5f8              PUSH     {r3-r7,lr}
;;;397    {
00034e  4604              MOV      r4,r0
000350  460d              MOV      r5,r1
;;;398    	unsigned char addrbyte,addrbit,tempdat;
;;;399    	
;;;400    	//com/segӦʾRAMַbit
;;;401    	addrbyte=seg/2*2;
000352  4620              MOV      r0,r4
000354  eb0471d0          ADD      r1,r4,r0,LSR #31
000358  1049              ASRS     r1,r1,#1
00035a  0649              LSLS     r1,r1,#25
00035c  0e0f              LSRS     r7,r1,#24
;;;402    	if((seg%2)==0)
00035e  eb0471d0          ADD      r1,r4,r0,LSR #31
000362  1049              ASRS     r1,r1,#1
000364  eba40141          SUB      r1,r4,r1,LSL #1
000368  b919              CBNZ     r1,|L1.882|
;;;403    		addrbit=(1<<com);
00036a  2001              MOVS     r0,#1
00036c  40a8              LSLS     r0,r0,r5
00036e  b2c6              UXTB     r6,r0
000370  e003              B        |L1.890|
                  |L1.882|
;;;404    	else
;;;405    		addrbit=(1<<(4+com));
000372  1d28              ADDS     r0,r5,#4
000374  2101              MOVS     r1,#1
000376  4081              LSLS     r1,r1,r0
000378  b2ce              UXTB     r6,r1
                  |L1.890|
;;;406    	tempdat=VKL128_dispram[seg/2]|addrbit;
00037a  4620              MOV      r0,r4
00037c  eb0471d0          ADD      r1,r4,r0,LSR #31
000380  1049              ASRS     r1,r1,#1
000382  4a26              LDR      r2,|L1.1052|
000384  5c51              LDRB     r1,[r2,r1]
000386  4331              ORRS     r1,r1,r6
000388  9100              STR      r1,[sp,#0]
;;;407    	VKL128_dispram[seg/2]=tempdat;
00038a  f89d1000          LDRB     r1,[sp,#0]
00038e  eb0472d0          ADD      r2,r4,r0,LSR #31
000392  1052              ASRS     r2,r2,#1
000394  4b21              LDR      r3,|L1.1052|
000396  5499              STRB     r1,[r3,r2]
;;;408    	WritenDataVKL128(addrbyte,&tempdat,1);		//8bitݶӦ2SEGseg/comӦbit17bitı
000398  2201              MOVS     r2,#1
00039a  4669              MOV      r1,sp
00039c  4638              MOV      r0,r7
00039e  f7fffffe          BL       WritenDataVKL128
;;;409    }
0003a2  bdf8              POP      {r3-r7,pc}
;;;410    /*******************************************************************************
                          ENDP

                  VKL128_DisDotOff PROC
;;;417    *******************************************************************************/
;;;418    void VKL128_DisDotOff(unsigned char seg,unsigned char com)
0003a4  b5f8              PUSH     {r3-r7,lr}
;;;419    {
0003a6  4604              MOV      r4,r0
0003a8  460d              MOV      r5,r1
;;;420    	unsigned char addrbyte,addrbit,tempdat;
;;;421    	
;;;422    	//com/segӦʾRAMַbit
;;;423    	addrbyte=seg/2*2;
0003aa  4620              MOV      r0,r4
0003ac  eb0471d0          ADD      r1,r4,r0,LSR #31
0003b0  1049              ASRS     r1,r1,#1
0003b2  0649              LSLS     r1,r1,#25
0003b4  0e0f              LSRS     r7,r1,#24
;;;424    	if((seg%2)==0)
0003b6  eb0471d0          ADD      r1,r4,r0,LSR #31
0003ba  1049              ASRS     r1,r1,#1
0003bc  eba40141          SUB      r1,r4,r1,LSL #1
0003c0  b919              CBNZ     r1,|L1.970|
;;;425    		addrbit=(1<<com);
0003c2  2001              MOVS     r0,#1
0003c4  40a8              LSLS     r0,r0,r5
0003c6  b2c6              UXTB     r6,r0
0003c8  e003              B        |L1.978|
                  |L1.970|
;;;426    	else
;;;427    		addrbit=(1<<(4+com));
0003ca  1d28              ADDS     r0,r5,#4
0003cc  2101              MOVS     r1,#1
0003ce  4081              LSLS     r1,r1,r0
0003d0  b2ce              UXTB     r6,r1
                  |L1.978|
;;;428    	tempdat=VKL128_dispram[seg/2]&(~addrbit);
0003d2  4620              MOV      r0,r4
0003d4  eb0471d0          ADD      r1,r4,r0,LSR #31
0003d8  1049              ASRS     r1,r1,#1
0003da  4a10              LDR      r2,|L1.1052|
0003dc  5c51              LDRB     r1,[r2,r1]
0003de  43b1              BICS     r1,r1,r6
0003e0  9100              STR      r1,[sp,#0]
;;;429    	VKL128_dispram[seg/2]=tempdat;
0003e2  f89d1000          LDRB     r1,[sp,#0]
0003e6  eb0472d0          ADD      r2,r4,r0,LSR #31
0003ea  1052              ASRS     r2,r2,#1
0003ec  4b0b              LDR      r3,|L1.1052|
0003ee  5499              STRB     r1,[r3,r2]
;;;430    	WritenDataVKL128(addrbyte,&tempdat,1);		//8bitݶӦ2SEGseg/comӦbit07bitı
0003f0  2201              MOVS     r2,#1
0003f2  4669              MOV      r1,sp
0003f4  4638              MOV      r0,r7
0003f6  f7fffffe          BL       WritenDataVKL128
;;;431    }
0003fa  bdf8              POP      {r3-r7,pc}
;;;432    /*******************************************************************************
                          ENDP

                  VKL128_Enter_PowerOff PROC
;;;438    *******************************************************************************/
;;;439    unsigned char VKL128_Enter_PowerOff(void)
0003fc  b500              PUSH     {lr}
;;;440    {		
;;;441    	VKL128_I2CStart();
0003fe  f7fffffe          BL       VKL128_I2CStart
;;;442    	VKL128_I2CWRCmd(VKL128_ADDRWR); 
000402  207c              MOVS     r0,#0x7c
000404  f7fffffe          BL       VKL128_I2CWRCmd
;;;443    	if( 1 == VKL128_I2CSlaveAck() )
000408  f7fffffe          BL       VKL128_I2CSlaveAck
00040c  2801              CMP      r0,#1
00040e  d107              BNE      |L1.1056|
;;;444    	{
;;;445    		VKL128_I2CStop();
000410  f7fffffe          BL       VKL128_I2CStop
;;;446    		return 1; 
000414  2001              MOVS     r0,#1
                  |L1.1046|
;;;447    	}
;;;448    	VKL128_I2CWRCmd(VKL128_LCD_OFF);		//ʾ
;;;449    	if( 1 == VKL128_I2CSlaveAck() )
;;;450    	{
;;;451    		VKL128_I2CStop();
;;;452    		return 1; 
;;;453    	}
;;;454    	VKL128_I2CStop();
;;;455      return 0; 
;;;456    }
000416  bd00              POP      {pc}
                  |L1.1048|
                          DCD      0x4000487c
                  |L1.1052|
                          DCD      VKL128_dispram
                  |L1.1056|
000420  20c0              MOVS     r0,#0xc0              ;448
000422  f7fffffe          BL       VKL128_I2CWRCmd
000426  f7fffffe          BL       VKL128_I2CSlaveAck
00042a  2801              CMP      r0,#1                 ;449
00042c  d103              BNE      |L1.1078|
00042e  f7fffffe          BL       VKL128_I2CStop
000432  2001              MOVS     r0,#1                 ;452
000434  e7ef              B        |L1.1046|
                  |L1.1078|
000436  f7fffffe          BL       VKL128_I2CStop
00043a  2000              MOVS     r0,#0                 ;455
00043c  e7eb              B        |L1.1046|
;;;457    /*******************************************************************************
                          ENDP

                  VKL128_InitSequence PROC
;;;479    *******************************************************************************/
;;;480    unsigned char VKL128_InitSequence(void)
00043e  b500              PUSH     {lr}
;;;481    {			
;;;482      //ϵʼʱ򣨲οֲϵ縴λʱͼͲ	
;;;483    	//ϵ100uSʼ
;;;484      Delay_nuS(100);
000440  2064              MOVS     r0,#0x64
000442  f7fffffe          BL       Delay_nuS
;;;485    	//STOPź
;;;486    	VKL128_I2CStop();
000446  f7fffffe          BL       VKL128_I2CStop
;;;487    	//STARTź
;;;488    	VKL128_I2CStart();
00044a  f7fffffe          BL       VKL128_I2CStart
;;;489    	//SLAVEַ(0x7C)
;;;490    	VKL128_I2CWRCmd(VKL128_ADDRWR); 
00044e  207c              MOVS     r0,#0x7c
000450  f7fffffe          BL       VKL128_I2CWRCmd
;;;491    	if( 1 == VKL128_I2CSlaveAck() )
000454  f7fffffe          BL       VKL128_I2CSlaveAck
000458  2801              CMP      r0,#1
00045a  d103              BNE      |L1.1124|
;;;492    	{
;;;493    		VKL128_I2CStop();	
00045c  f7fffffe          BL       VKL128_I2CStop
;;;494    		return 1;
000460  2001              MOVS     r0,#1
                  |L1.1122|
;;;495    	}
;;;496    	//ϵͳ(λ)
;;;497    	VKL128_I2CWRCmd(VKL128_SOFTRST);
;;;498    	if( 1 == VKL128_I2CSlaveAck() )
;;;499    	{
;;;500    		VKL128_I2CStop();	
;;;501    		return 1;
;;;502    	}
;;;503    	//ʾ(֡Ƶģʽʽ)ΪʵƷֵο
;;;504    	//VKL128_I2CWRCmd(VKL128_FR80HZ|VKL128_SRNOR|VKL128_LINER);  	//ϵĬ 	VDD=5V:18.2uA  	VDD=3.3V:13uA
;;;505    	VKL128_I2CWRCmd(VKL128_FR53HZ|VKL128_SRPM1|VKL128_FRAMER);  //ʡ 		VDD=5V:9.1uA  VDD=3.3V:6.8uA
;;;506    	//VKL128_I2CWRCmd(VKL128_FR80HZ|VKL128_SRHP|VKL128_LINER);  	// 			VDD=5V:20uA  	VDD=3.3V:15uA 
;;;507    	if( 1 == VKL128_I2CSlaveAck() )
;;;508    	{
;;;509    		VKL128_I2CStop();	
;;;510    		return 1;
;;;511    	}
;;;512      //ģʽ
;;;513    	VKL128_I2CWRCmd(VKL128_BIAS_1_3|VKL128_LCD_ON);		//1/3bias,ʾ 
;;;514    	//VKL128_I2CWRCmd(VKL128_BIAS_1_2|VKL128_LCD_ON);		//1/2bias,ʾ 
;;;515    	if( 1 == VKL128_I2CSlaveAck() )
;;;516    	{
;;;517    		VKL128_I2CStop();	
;;;518    		return 1;
;;;519    	}
;;;520    	//STOPź
;;;521    	VKL128_I2CStop();	
;;;522    		
;;;523      return  0; 
;;;524    }
000462  bd00              POP      {pc}
                  |L1.1124|
000464  20ea              MOVS     r0,#0xea              ;497
000466  f7fffffe          BL       VKL128_I2CWRCmd
00046a  f7fffffe          BL       VKL128_I2CSlaveAck
00046e  2801              CMP      r0,#1                 ;498
000470  d103              BNE      |L1.1146|
000472  f7fffffe          BL       VKL128_I2CStop
000476  2001              MOVS     r0,#1                 ;501
000478  e7f3              B        |L1.1122|
                  |L1.1146|
00047a  20bc              MOVS     r0,#0xbc              ;505
00047c  f7fffffe          BL       VKL128_I2CWRCmd
000480  f7fffffe          BL       VKL128_I2CSlaveAck
000484  2801              CMP      r0,#1                 ;507
000486  d103              BNE      |L1.1168|
000488  f7fffffe          BL       VKL128_I2CStop
00048c  2001              MOVS     r0,#1                 ;510
00048e  e7e8              B        |L1.1122|
                  |L1.1168|
000490  20c8              MOVS     r0,#0xc8              ;513
000492  f7fffffe          BL       VKL128_I2CWRCmd
000496  f7fffffe          BL       VKL128_I2CSlaveAck
00049a  2801              CMP      r0,#1                 ;515
00049c  d103              BNE      |L1.1190|
00049e  f7fffffe          BL       VKL128_I2CStop
0004a2  2001              MOVS     r0,#1                 ;518
0004a4  e7dd              B        |L1.1122|
                  |L1.1190|
0004a6  f7fffffe          BL       VKL128_I2CStop
0004aa  2000              MOVS     r0,#0                 ;523
0004ac  e7d9              B        |L1.1122|
;;;525    /*******************************************************************************
                          ENDP

                  VKL128_Exit_PowerOff PROC
;;;463    *******************************************************************************/
;;;464    unsigned char VKL128_Exit_PowerOff(void)
0004ae  b510              PUSH     {r4,lr}
;;;465    {	
;;;466    	unsigned char errorflag; 
;;;467    	
;;;468    	//˳ģʽ³ʼʱ
;;;469    	errorflag=VKL128_InitSequence();
0004b0  f7fffffe          BL       VKL128_InitSequence
0004b4  4604              MOV      r4,r0
;;;470    	
;;;471      return(errorflag);
0004b6  4620              MOV      r0,r4
;;;472    }
0004b8  bd10              POP      {r4,pc}
;;;473    /*******************************************************************************
                          ENDP

                  VKL128_Lowlevel_Init PROC
;;;531    *******************************************************************************/
;;;532    void VKL128_Lowlevel_Init(void)
0004ba  b510              PUSH     {r4,lr}
;;;533    {
;;;534    	//ͨߵƽͬӵƽת·
;;;535    	//˺ݿͻƬӦ޸	
;;;536    	GPIO_SetMode(VKL128_SCL_PORT, VKL128_SCL_PIN, GPIO_MODE_OUTPUT);
0004bc  2201              MOVS     r2,#1
0004be  03d1              LSLS     r1,r2,#15
0004c0  4864              LDR      r0,|L1.1620|
0004c2  f7fffffe          BL       GPIO_SetMode
;;;537    	GPIO_SetMode(VKL128_SDA_PORT, VKL128_SDA_PIN, GPIO_MODE_QUASI);
0004c6  2203              MOVS     r2,#3
0004c8  2120              MOVS     r1,#0x20
0004ca  4862              LDR      r0,|L1.1620|
0004cc  f7fffffe          BL       GPIO_SetMode
;;;538    	
;;;539      //I2C߿Ϊߵƽ	
;;;540    	VKL128_SCL_H();  
0004d0  2001              MOVS     r0,#1
0004d2  4961              LDR      r1,|L1.1624|
0004d4  6008              STR      r0,[r1,#0]
;;;541    	VKL128_SDA_H(); 	
0004d6  4960              LDR      r1,|L1.1624|
0004d8  3928              SUBS     r1,r1,#0x28
0004da  6008              STR      r0,[r1,#0]
;;;542    }
0004dc  bd10              POP      {r4,pc}
;;;543    /*******************************************************************************
                          ENDP

                  VKL128_Init PROC
;;;549    *******************************************************************************/
;;;550    void VKL128_Init(void)
0004de  b510              PUSH     {r4,lr}
;;;551    {	
;;;552    	//ܽøݿͻƬӦ޸
;;;553    	VKL128_Lowlevel_Init();
0004e0  f7fffffe          BL       VKL128_Lowlevel_Init
;;;554    	//ʼʱ
;;;555    	VKL128_InitSequence();
0004e4  f7fffffe          BL       VKL128_InitSequence
;;;556    }
0004e8  bd10              POP      {r4,pc}
;;;557    /*******************************************************************************
                          ENDP

                  VKL128_Main PROC
;;;563    *******************************************************************************/
;;;564    void VKL128_Main(void)
0004ea  f7fffffe          BL       VKL128_Init
;;;565    {	
;;;566    	VKL128_Init();
;;;567    	
;;;568    	//ѡⲿʱ(OSCI)ƵΪ32KHz(ʵ֡ƵƵ)
;;;569    	//WriteCmdVKL128(VKL128_EXTCLK); //ʾַʱVKL128_ADDRWR5bit0һҪ1
;;;570    	
;;;571    	//˸
;;;572    	//WriteCmdVKL128(VKL128_BLKCTL_05HZ); //˸Ƶ0.5Hz
;;;573    	//WriteCmdVKL128(VKL128_BLKCTL_1HZ); 	//˸Ƶ1Hz
;;;574    	WriteCmdVKL128(VKL128_BLKCTL_2HZ); 	//˸Ƶ2Hz
0004ee  20f3              MOVS     r0,#0xf3
0004f0  f7fffffe          BL       WriteCmdVKL128
;;;575    	//WriteCmdVKL128(VKL128_BLKCTL_OFF);	//˸ر
;;;576    	
;;;577    	//ȫǿƿ
;;;578    	WriteCmdVKL128(VKL128_APCTL_ALLON2);	
0004f4  20fe              MOVS     r0,#0xfe
0004f6  f7fffffe          BL       WriteCmdVKL128
;;;579    	Delay_nmS(3000);					//ʱ
0004fa  f64030b8          MOV      r0,#0xbb8
0004fe  f7fffffe          BL       Delay_nmS
;;;580    	//ȫǿƹ
;;;581    	WriteCmdVKL128(VKL128_APCTL_ALLOFF1);
000502  20fd              MOVS     r0,#0xfd
000504  f7fffffe          BL       WriteCmdVKL128
;;;582    	Delay_nmS(1000);					//ʱ
000508  f44f707a          MOV      r0,#0x3e8
00050c  f7fffffe          BL       Delay_nmS
;;;583    	
;;;584    	//ȫǿȡ,ָ
;;;585    	WriteCmdVKL128(VKL128_APCTL_NORMAL);
000510  20fc              MOVS     r0,#0xfc
000512  f7fffffe          BL       WriteCmdVKL128
;;;586    	WriteCmdVKL128(VKL128_BLKCTL_OFF);	//˸ر
000516  20f0              MOVS     r0,#0xf0
000518  f7fffffe          BL       WriteCmdVKL128
;;;587    	
;;;588    	VKL128_DisAll(0x00);
00051c  2000              MOVS     r0,#0
00051e  f7fffffe          BL       VKL128_DisAll
;;;589    	while(1)
000522  e096              B        |L1.1618|
                  |L1.1316|
;;;590    	{		
;;;591    		//LCDȫ
;;;592    		VKL128_DisAll(0xFF);			
000524  20ff              MOVS     r0,#0xff
000526  f7fffffe          BL       VKL128_DisAll
;;;593    		Delay_nmS(3000);					//ʱ
00052a  f64030b8          MOV      r0,#0xbb8
00052e  f7fffffe          BL       Delay_nmS
;;;594    		
;;;595    		//LCDȫ
;;;596    		VKL128_DisAll(0x00);			
000532  2000              MOVS     r0,#0
000534  f7fffffe          BL       VKL128_DisAll
;;;597    		Delay_nmS(3000);					//ʱ
000538  f64030b8          MOV      r0,#0xbb8
00053c  f7fffffe          BL       Delay_nmS
;;;598    	
;;;599    		//LCD
;;;600    		VKL128_DisAll(0x55);			
000540  2055              MOVS     r0,#0x55
000542  f7fffffe          BL       VKL128_DisAll
;;;601    		ReadnDataVKL128(0,VKL128_readbuf,16);	//RAM
000546  2210              MOVS     r2,#0x10
000548  4944              LDR      r1,|L1.1628|
00054a  2000              MOVS     r0,#0
00054c  f7fffffe          BL       ReadnDataVKL128
;;;602    		Delay_nmS(1500);					//ʱ
000550  f24050dc          MOV      r0,#0x5dc
000554  f7fffffe          BL       Delay_nmS
;;;603    		VKL128_DisAll(0xAA);			
000558  20aa              MOVS     r0,#0xaa
00055a  f7fffffe          BL       VKL128_DisAll
;;;604    		ReadnDataVKL128(0,VKL128_readbuf,16);	//RAM
00055e  2210              MOVS     r2,#0x10
000560  493e              LDR      r1,|L1.1628|
000562  2000              MOVS     r0,#0
000564  f7fffffe          BL       ReadnDataVKL128
;;;605    		Delay_nmS(1500);					//ʱ
000568  f24050dc          MOV      r0,#0x5dc
00056c  f7fffffe          BL       Delay_nmS
;;;606    		
;;;607    		//
;;;608    		VKL128_DisAll(0x00);			//LCDȫ		
000570  2000              MOVS     r0,#0
000572  f7fffffe          BL       VKL128_DisAll
;;;609    		VKL128_Enter_PowerOff();	//ģʽ
000576  f7fffffe          BL       VKL128_Enter_PowerOff
;;;610    		Delay_nmS(5000);					//ʱ5S		
00057a  f2413088          MOV      r0,#0x1388
00057e  f7fffffe          BL       Delay_nmS
;;;611    		VKL128_Exit_PowerOff();	//˳ģʽ
000582  f7fffffe          BL       VKL128_Exit_PowerOff
;;;612    				
;;;613    		//LCD
;;;614    		VKL128_DisAll(0x00);			//LCDȫ
000586  2000              MOVS     r0,#0
000588  f7fffffe          BL       VKL128_DisAll
;;;615    		Delay_nmS(500);						//ʱ
00058c  f44f70fa          MOV      r0,#0x1f4
000590  f7fffffe          BL       Delay_nmS
;;;616    		for(VKL128_segi=0;VKL128_segi<32;VKL128_segi++)//seg0-31
000594  2000              MOVS     r0,#0
000596  4932              LDR      r1,|L1.1632|
000598  7008              STRB     r0,[r1,#0]
00059a  e021              B        |L1.1504|
                  |L1.1436|
;;;617    		{
;;;618    			for(VKL128_comi=0;VKL128_comi<4;VKL128_comi++)//com0-3
00059c  2000              MOVS     r0,#0
00059e  4931              LDR      r1,|L1.1636|
0005a0  7008              STRB     r0,[r1,#0]
0005a2  e014              B        |L1.1486|
                  |L1.1444|
;;;619    			{
;;;620    				VKL128_DisDotOn(VKL128_segi,VKL128_comi);		//LCD
0005a4  482f              LDR      r0,|L1.1636|
0005a6  7801              LDRB     r1,[r0,#0]  ; VKL128_comi
0005a8  482d              LDR      r0,|L1.1632|
0005aa  7800              LDRB     r0,[r0,#0]  ; VKL128_segi
0005ac  f7fffffe          BL       VKL128_DisDotOn
;;;621    				Delay_nmS(300);				//ʱ
0005b0  f44f7096          MOV      r0,#0x12c
0005b4  f7fffffe          BL       Delay_nmS
;;;622    				VKL128_DisDotOff(VKL128_segi,VKL128_comi);		//ϵʵֵδ˳
0005b8  482a              LDR      r0,|L1.1636|
0005ba  7801              LDRB     r1,[r0,#0]  ; VKL128_comi
0005bc  4828              LDR      r0,|L1.1632|
0005be  7800              LDRB     r0,[r0,#0]  ; VKL128_segi
0005c0  f7fffffe          BL       VKL128_DisDotOff
0005c4  4827              LDR      r0,|L1.1636|
0005c6  7800              LDRB     r0,[r0,#0]            ;618  ; VKL128_comi
0005c8  1c40              ADDS     r0,r0,#1              ;618
0005ca  4926              LDR      r1,|L1.1636|
0005cc  7008              STRB     r0,[r1,#0]            ;618
                  |L1.1486|
0005ce  4825              LDR      r0,|L1.1636|
0005d0  7800              LDRB     r0,[r0,#0]            ;618  ; VKL128_comi
0005d2  2804              CMP      r0,#4                 ;618
0005d4  dbe6              BLT      |L1.1444|
0005d6  4822              LDR      r0,|L1.1632|
0005d8  7800              LDRB     r0,[r0,#0]            ;616  ; VKL128_segi
0005da  1c40              ADDS     r0,r0,#1              ;616
0005dc  4920              LDR      r1,|L1.1632|
0005de  7008              STRB     r0,[r1,#0]            ;616
                  |L1.1504|
0005e0  481f              LDR      r0,|L1.1632|
0005e2  7800              LDRB     r0,[r0,#0]            ;616  ; VKL128_segi
0005e4  2820              CMP      r0,#0x20              ;616
0005e6  dbd9              BLT      |L1.1436|
;;;623    			}
;;;624    		}
;;;625    		
;;;626    		//LCDر
;;;627    		VKL128_DisAll(0xff);			//LCDȫ
0005e8  20ff              MOVS     r0,#0xff
0005ea  f7fffffe          BL       VKL128_DisAll
;;;628    		Delay_nmS(500);						//ʱ
0005ee  f44f70fa          MOV      r0,#0x1f4
0005f2  f7fffffe          BL       Delay_nmS
;;;629    		for(VKL128_segi=0;VKL128_segi<32;VKL128_segi++)//seg0-31
0005f6  2000              MOVS     r0,#0
0005f8  4919              LDR      r1,|L1.1632|
0005fa  7008              STRB     r0,[r1,#0]
0005fc  e021              B        |L1.1602|
                  |L1.1534|
;;;630    		{
;;;631    			for(VKL128_comi=0;VKL128_comi<4;VKL128_comi++)//com0-3
0005fe  2000              MOVS     r0,#0
000600  4918              LDR      r1,|L1.1636|
000602  7008              STRB     r0,[r1,#0]
000604  e014              B        |L1.1584|
                  |L1.1542|
;;;632    			{
;;;633    				VKL128_DisDotOff(VKL128_segi,VKL128_comi);		//LCDر
000606  4817              LDR      r0,|L1.1636|
000608  7801              LDRB     r1,[r0,#0]  ; VKL128_comi
00060a  4815              LDR      r0,|L1.1632|
00060c  7800              LDRB     r0,[r0,#0]  ; VKL128_segi
00060e  f7fffffe          BL       VKL128_DisDotOff
;;;634    				Delay_nmS(300);				//ʱ
000612  f44f7096          MOV      r0,#0x12c
000616  f7fffffe          BL       Delay_nmS
;;;635    				VKL128_DisDotOn(VKL128_segi,VKL128_comi);		//ϵرպʵֵرգδ˳ر
00061a  4812              LDR      r0,|L1.1636|
00061c  7801              LDRB     r1,[r0,#0]  ; VKL128_comi
00061e  4810              LDR      r0,|L1.1632|
000620  7800              LDRB     r0,[r0,#0]  ; VKL128_segi
000622  f7fffffe          BL       VKL128_DisDotOn
000626  480f              LDR      r0,|L1.1636|
000628  7800              LDRB     r0,[r0,#0]            ;631  ; VKL128_comi
00062a  1c40              ADDS     r0,r0,#1              ;631
00062c  490d              LDR      r1,|L1.1636|
00062e  7008              STRB     r0,[r1,#0]            ;631
                  |L1.1584|
000630  480c              LDR      r0,|L1.1636|
000632  7800              LDRB     r0,[r0,#0]            ;631  ; VKL128_comi
000634  2804              CMP      r0,#4                 ;631
000636  dbe6              BLT      |L1.1542|
000638  4809              LDR      r0,|L1.1632|
00063a  7800              LDRB     r0,[r0,#0]            ;629  ; VKL128_segi
00063c  1c40              ADDS     r0,r0,#1              ;629
00063e  4908              LDR      r1,|L1.1632|
000640  7008              STRB     r0,[r1,#0]            ;629
                  |L1.1602|
000642  4807              LDR      r0,|L1.1632|
000644  7800              LDRB     r0,[r0,#0]            ;629  ; VKL128_segi
000646  2820              CMP      r0,#0x20              ;629
000648  dbd9              BLT      |L1.1534|
;;;636    			}
;;;637    		}		
;;;638    		Delay_nmS(1000);					//ʱ
00064a  f44f707a          MOV      r0,#0x3e8
00064e  f7fffffe          BL       Delay_nmS
                  |L1.1618|
000652  e767              B        |L1.1316|
;;;639    	}
;;;640    }
;;;641    /************************END OF FILE****/
                          ENDP

                  |L1.1620|
                          DCD      0x40004040
                  |L1.1624|
                          DCD      0x4000487c
                  |L1.1628|
                          DCD      VKL128_readbuf
                  |L1.1632|
                          DCD      VKL128_segi
                  |L1.1636|
                          DCD      VKL128_comi

                          AREA ||.bss||, DATA, NOINIT, ALIGN=0

                  VKL128_dispram
                          %        16
                  VKL128_readbuf
                          %        16

                          AREA ||.data||, DATA, ALIGN=0

                  VKL128_segi
000000  00                DCB      0x00
                  VKL128_comi
000001  00                DCB      0x00

;*** Start embedded assembler ***

#line 1 "..\\lcd_driver\\VKL128_IO_I2C_QUASI.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___21_VKL128_IO_I2C_QUASI_c_f70de489____REV16|
#line 114 "..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___21_VKL128_IO_I2C_QUASI_c_f70de489____REV16| PROC
#line 115

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___21_VKL128_IO_I2C_QUASI_c_f70de489____REVSH|
#line 128
|__asm___21_VKL128_IO_I2C_QUASI_c_f70de489____REVSH| PROC
#line 129

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
