; generated by Component: ARM Compiler 5.05 update 2 (build 169) Tool: ArmCC [4d0f38]
; commandline ArmCC [--list --debug -c --asm --interleave -o.\obj\main.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\main.d --cpu=Cortex-M4.fp --apcs=interwork -O0 --diag_suppress=9931 -I..\..\..\Library\CMSIS\Include -I..\..\..\Library\Device\Nuvoton\M451Series\Include -I..\..\..\Library\StdDriver\inc -I..\Bsp -I..\User -I..\lcd_driver -I..\exti_driver -I..\led_driver -I..\touch -I..\dotmatix_lcd -I..\KH -ID:\\A\LCD\͹ϵ_VKL\VKL\VKL144B_TESTCODE\project\VKL144_FUNC\Keil\RTE -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\4.3.0\CMSIS\Include -D__UVISION_VERSION=515 -D_RTE_ --omf_browse=.\obj\main.crf ..\User\main.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  I2C0_IRQHandler PROC
;;;49     /*---------------------------------------------------------------------------------------------------------*/
;;;50     void I2C0_IRQHandler(void)
000000  b510              PUSH     {r4,lr}
;;;51     {
;;;52         unsigned int status;
;;;53     
;;;54         status = I2C_GET_STATUS(I2C0);
000002  48f3              LDR      r0,|L1.976|
000004  68c4              LDR      r4,[r0,#0xc]
;;;55         if(I2C_GET_TIMEOUT_FLAG(I2C0))
000006  6940              LDR      r0,[r0,#0x14]
000008  f0000001          AND      r0,r0,#1
00000c  b118              CBZ      r0,|L1.22|
;;;56         {
;;;57             /* Clear I2C0 Timeout Flag */
;;;58             I2C_ClearTimeoutFlag(I2C0);
00000e  48f0              LDR      r0,|L1.976|
000010  f7fffffe          BL       I2C_ClearTimeoutFlag
000014  e006              B        |L1.36|
                  |L1.22|
;;;59         }
;;;60         else
;;;61         {
;;;62             if(i2c0handlerflag != NULL)
000016  48ef              LDR      r0,|L1.980|
000018  6800              LDR      r0,[r0,#0]  ; i2c0handlerflag
00001a  b118              CBZ      r0,|L1.36|
;;;63                 i2c0handlerflag(status);
00001c  4620              MOV      r0,r4
00001e  49ed              LDR      r1,|L1.980|
000020  6809              LDR      r1,[r1,#0]  ; i2c0handlerflag
000022  4788              BLX      r1
                  |L1.36|
;;;64         }
;;;65     }
000024  bd10              POP      {r4,pc}
;;;66     
                          ENDP

                  I2C_MasterRx PROC
;;;69     /*---------------------------------------------------------------------------------------------------------*/
;;;70     void I2C_MasterRx(unsigned int rxstatus)
000026  b510              PUSH     {r4,lr}
;;;71     {
000028  4604              MOV      r4,r0
;;;72         if(rxstatus == 0x08)                       /* START has been transmitted and prepare SLA+W */
00002a  2c08              CMP      r4,#8
00002c  d10a              BNE      |L1.68|
;;;73         {
;;;74             I2C_SET_DATA(I2C0, (VKL144B_ADDR << 1));    /* Write SLA+W to Register I2CDAT */
00002e  207c              MOVS     r0,#0x7c
000030  49e7              LDR      r1,|L1.976|
000032  6088              STR      r0,[r1,#8]
;;;75             I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);
000034  4608              MOV      r0,r1
000036  6800              LDR      r0,[r0,#0]
000038  f020003c          BIC      r0,r0,#0x3c
00003c  f0400008          ORR      r0,r0,#8
000040  6008              STR      r0,[r1,#0]
000042  e055              B        |L1.240|
                  |L1.68|
;;;76         }
;;;77         else if(rxstatus == 0x18)                  /* SLA+W has been transmitted and ACK has been received */
000044  2c18              CMP      r4,#0x18
000046  d111              BNE      |L1.108|
;;;78         {
;;;79     			  I2C_SET_DATA(I2C0, i2crdtx[txcnt++]);
000048  48e3              LDR      r0,|L1.984|
00004a  7801              LDRB     r1,[r0,#0]  ; txcnt
00004c  7800              LDRB     r0,[r0,#0]  ; txcnt
00004e  1c40              ADDS     r0,r0,#1
000050  4ae1              LDR      r2,|L1.984|
000052  7010              STRB     r0,[r2,#0]
000054  48e1              LDR      r0,|L1.988|
000056  5c40              LDRB     r0,[r0,r1]
000058  49dd              LDR      r1,|L1.976|
00005a  6088              STR      r0,[r1,#8]
;;;80             I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);
00005c  4608              MOV      r0,r1
00005e  6800              LDR      r0,[r0,#0]
000060  f020003c          BIC      r0,r0,#0x3c
000064  f0400008          ORR      r0,r0,#8
000068  6008              STR      r0,[r1,#0]
00006a  e041              B        |L1.240|
                  |L1.108|
;;;81         }
;;;82         else if(rxstatus == 0x20)                  /* SLA+W has been transmitted and NACK has been received */
00006c  2c20              CMP      r4,#0x20
00006e  d10b              BNE      |L1.136|
;;;83         {
;;;84             I2C_STOP(I2C0);
000070  48d7              LDR      r0,|L1.976|
000072  f7fffffe          BL       I2C_STOP
;;;85             I2C_START(I2C0);
000076  48d6              LDR      r0,|L1.976|
000078  6800              LDR      r0,[r0,#0]
00007a  f0200008          BIC      r0,r0,#8
00007e  f0400020          ORR      r0,r0,#0x20
000082  49d3              LDR      r1,|L1.976|
000084  6008              STR      r0,[r1,#0]
000086  e033              B        |L1.240|
                  |L1.136|
;;;86         }
;;;87         else if(rxstatus == 0x28)                  /* DATA has been transmitted and ACK has been received */
000088  2c28              CMP      r4,#0x28
00008a  d108              BNE      |L1.158|
;;;88         {
;;;89     			 I2C_SET_CONTROL_REG(I2C0, I2C_CTL_STA_SI);  //ݡSR START
00008c  48d0              LDR      r0,|L1.976|
00008e  6800              LDR      r0,[r0,#0]
000090  f020003c          BIC      r0,r0,#0x3c
000094  f0400028          ORR      r0,r0,#0x28
000098  49cd              LDR      r1,|L1.976|
00009a  6008              STR      r0,[r1,#0]
00009c  e028              B        |L1.240|
                  |L1.158|
;;;90         }
;;;91         else if(rxstatus == 0x10)                  /* Repeat START has been transmitted and prepare SLA+R */
00009e  2c10              CMP      r4,#0x10
0000a0  d10a              BNE      |L1.184|
;;;92         {
;;;93             I2C_SET_DATA(I2C0, ((VKL144B_ADDR << 1) | 0x01));   /* Write SLA+R to Register I2CDAT */
0000a2  207d              MOVS     r0,#0x7d
0000a4  49ca              LDR      r1,|L1.976|
0000a6  6088              STR      r0,[r1,#8]
;;;94             I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);
0000a8  4608              MOV      r0,r1
0000aa  6800              LDR      r0,[r0,#0]
0000ac  f020003c          BIC      r0,r0,#0x3c
0000b0  f0400008          ORR      r0,r0,#8
0000b4  6008              STR      r0,[r1,#0]
0000b6  e01b              B        |L1.240|
                  |L1.184|
;;;95         }
;;;96         else if(rxstatus == 0x40)                  /* SLA+R has been transmitted and ACK has been received */
0000b8  2c40              CMP      r4,#0x40
0000ba  d108              BNE      |L1.206|
;;;97         {
;;;98             I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);
0000bc  48c4              LDR      r0,|L1.976|
0000be  6800              LDR      r0,[r0,#0]
0000c0  f020003c          BIC      r0,r0,#0x3c
0000c4  f0400008          ORR      r0,r0,#8
0000c8  49c1              LDR      r1,|L1.976|
0000ca  6008              STR      r0,[r1,#0]
0000cc  e010              B        |L1.240|
                  |L1.206|
;;;99         }
;;;100        else if(rxstatus == 0x58)                  /* DATA has been received and NACK has been returned */
0000ce  2c58              CMP      r4,#0x58
0000d0  d10e              BNE      |L1.240|
;;;101        {
;;;102    			i2crdrx = (unsigned char) I2C_GET_DATA(I2C0);
0000d2  48bf              LDR      r0,|L1.976|
0000d4  6880              LDR      r0,[r0,#8]
0000d6  49c2              LDR      r1,|L1.992|
0000d8  7008              STRB     r0,[r1,#0]
;;;103    			I2C_SET_CONTROL_REG(I2C0, I2C_CTL_STO_SI); //STOP
0000da  48bd              LDR      r0,|L1.976|
0000dc  6800              LDR      r0,[r0,#0]
0000de  f020003c          BIC      r0,r0,#0x3c
0000e2  f0400018          ORR      r0,r0,#0x18
0000e6  49ba              LDR      r1,|L1.976|
0000e8  6008              STR      r0,[r1,#0]
;;;104    			endflag = 1;
0000ea  2001              MOVS     r0,#1
0000ec  49bd              LDR      r1,|L1.996|
0000ee  7008              STRB     r0,[r1,#0]
                  |L1.240|
;;;105        }
;;;106        else
;;;107        {
;;;108            /* TO DO */
;;;109            //rxstatusis NOT processed
;;;110        }
;;;111    }
0000f0  bd10              POP      {r4,pc}
;;;112    
                          ENDP

                  I2C_MasterTx PROC
;;;115    /*---------------------------------------------------------------------------------------------------------*/
;;;116    void I2C_MasterTx(unsigned int txstatus)
0000f2  b510              PUSH     {r4,lr}
;;;117    {
0000f4  4604              MOV      r4,r0
;;;118        if(txstatus == 0x08)                       /* START has been transmitted */
0000f6  2c08              CMP      r4,#8
0000f8  d10a              BNE      |L1.272|
;;;119        {
;;;120            I2C_SET_DATA(I2C0, VKL144B_ADDR << 1);    /* Write SLA+W to Register I2CDAT */
0000fa  207c              MOVS     r0,#0x7c
0000fc  49b4              LDR      r1,|L1.976|
0000fe  6088              STR      r0,[r1,#8]
;;;121            I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);
000100  4608              MOV      r0,r1
000102  6800              LDR      r0,[r0,#0]
000104  f020003c          BIC      r0,r0,#0x3c
000108  f0400008          ORR      r0,r0,#8
00010c  6008              STR      r0,[r1,#0]
00010e  e048              B        |L1.418|
                  |L1.272|
;;;122        }
;;;123        else if(txstatus == 0x18)                  /* SLA+W has been transmitted and ACK has been received */
000110  2c18              CMP      r4,#0x18
000112  d111              BNE      |L1.312|
;;;124        {
;;;125            I2C_SET_DATA(I2C0, i2cwrbuf[txcnt++]);
000114  48b0              LDR      r0,|L1.984|
000116  7801              LDRB     r1,[r0,#0]  ; txcnt
000118  7800              LDRB     r0,[r0,#0]  ; txcnt
00011a  1c40              ADDS     r0,r0,#1
00011c  4aae              LDR      r2,|L1.984|
00011e  7010              STRB     r0,[r2,#0]
000120  48b1              LDR      r0,|L1.1000|
000122  5c40              LDRB     r0,[r0,r1]
000124  49aa              LDR      r1,|L1.976|
000126  6088              STR      r0,[r1,#8]
;;;126            I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);
000128  4608              MOV      r0,r1
00012a  6800              LDR      r0,[r0,#0]
00012c  f020003c          BIC      r0,r0,#0x3c
000130  f0400008          ORR      r0,r0,#8
000134  6008              STR      r0,[r1,#0]
000136  e034              B        |L1.418|
                  |L1.312|
;;;127        }
;;;128        else if(txstatus == 0x20)                  /* SLA+W has been transmitted and NACK has been received */
000138  2c20              CMP      r4,#0x20
00013a  d10b              BNE      |L1.340|
;;;129        {
;;;130            I2C_STOP(I2C0);
00013c  48a4              LDR      r0,|L1.976|
00013e  f7fffffe          BL       I2C_STOP
;;;131            I2C_START(I2C0);
000142  48a3              LDR      r0,|L1.976|
000144  6800              LDR      r0,[r0,#0]
000146  f0200008          BIC      r0,r0,#8
00014a  f0400020          ORR      r0,r0,#0x20
00014e  49a0              LDR      r1,|L1.976|
000150  6008              STR      r0,[r1,#0]
000152  e026              B        |L1.418|
                  |L1.340|
;;;132        }
;;;133        else if(txstatus == 0x28)                  /* DATA has been transmitted and ACK has been received */
000154  2c28              CMP      r4,#0x28
000156  d123              BNE      |L1.416|
;;;134        {
;;;135            if(txcnt != txlen)
000158  489f              LDR      r0,|L1.984|
00015a  7800              LDRB     r0,[r0,#0]  ; txcnt
00015c  49a3              LDR      r1,|L1.1004|
00015e  7809              LDRB     r1,[r1,#0]  ; txlen
000160  4288              CMP      r0,r1
000162  d011              BEQ      |L1.392|
;;;136            {
;;;137                I2C_SET_DATA(I2C0, i2cwrbuf[txcnt++]);
000164  489c              LDR      r0,|L1.984|
000166  7801              LDRB     r1,[r0,#0]  ; txcnt
000168  7800              LDRB     r0,[r0,#0]  ; txcnt
00016a  1c40              ADDS     r0,r0,#1
00016c  4a9a              LDR      r2,|L1.984|
00016e  7010              STRB     r0,[r2,#0]
000170  489d              LDR      r0,|L1.1000|
000172  5c40              LDRB     r0,[r0,r1]
000174  4996              LDR      r1,|L1.976|
000176  6088              STR      r0,[r1,#8]
;;;138                I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);
000178  4608              MOV      r0,r1
00017a  6800              LDR      r0,[r0,#0]
00017c  f020003c          BIC      r0,r0,#0x3c
000180  f0400008          ORR      r0,r0,#8
000184  6008              STR      r0,[r1,#0]
000186  e00c              B        |L1.418|
                  |L1.392|
;;;139            }
;;;140            else
;;;141            {
;;;142                I2C_SET_CONTROL_REG(I2C0, I2C_CTL_STO_SI);
000188  4891              LDR      r0,|L1.976|
00018a  6800              LDR      r0,[r0,#0]
00018c  f020003c          BIC      r0,r0,#0x3c
000190  f0400018          ORR      r0,r0,#0x18
000194  498e              LDR      r1,|L1.976|
000196  6008              STR      r0,[r1,#0]
;;;143                endflag = 1;
000198  2001              MOVS     r0,#1
00019a  4992              LDR      r1,|L1.996|
00019c  7008              STRB     r0,[r1,#0]
00019e  e000              B        |L1.418|
                  |L1.416|
;;;144            }
;;;145        }
;;;146        else
;;;147        {
;;;148           /* TO DO */
;;;149          //txstatus is NOT processed
;;;150    			__nop();
0001a0  bf00              NOP      
                  |L1.418|
;;;151        }
;;;152    }
0001a2  bd10              POP      {r4,pc}
;;;153    
                          ENDP

                  loopshift_left8 PROC
;;;160    *******************************************************************************/
;;;161    unsigned char loopshift_left8(unsigned char dat)
0001a4  b510              PUSH     {r4,lr}
;;;162    {
0001a6  4601              MOV      r1,r0
;;;163    	unsigned char i,retval,datval;
;;;164    	
;;;165    	datval=dat;
0001a8  460a              MOV      r2,r1
;;;166    	retval=0;
0001aa  2000              MOVS     r0,#0
;;;167    	for(i=0;i<8;i++)
0001ac  2300              MOVS     r3,#0
0001ae  e00a              B        |L1.454|
                  |L1.432|
;;;168    	{
;;;169    		retval>>=1;
0001b0  1040              ASRS     r0,r0,#1
;;;170    		if((datval&0x80)==0x80)
0001b2  f0020480          AND      r4,r2,#0x80
0001b6  2c80              CMP      r4,#0x80
0001b8  d101              BNE      |L1.446|
;;;171    			retval|=0x80;
0001ba  f0400080          ORR      r0,r0,#0x80
                  |L1.446|
;;;172    		datval<<=1;
0001be  0654              LSLS     r4,r2,#25
0001c0  0e22              LSRS     r2,r4,#24
0001c2  1c5c              ADDS     r4,r3,#1              ;167
0001c4  b2e3              UXTB     r3,r4                 ;167
                  |L1.454|
0001c6  2b08              CMP      r3,#8                 ;167
0001c8  dbf2              BLT      |L1.432|
;;;173    	}
;;;174    	return retval;
;;;175    }
0001ca  bd10              POP      {r4,pc}
;;;176    /*******************************************************************************
                          ENDP

                  VKL144B_I2C_WRDat PROC
;;;182    *******************************************************************************/
;;;183    void VKL144B_I2C_WRDat(unsigned char Addr,unsigned char *Databuf,unsigned char cnt)
0001cc  b5f0              PUSH     {r4-r7,lr}
;;;184    {
0001ce  4605              MOV      r5,r0
0001d0  460e              MOV      r6,r1
0001d2  4617              MOV      r7,r2
;;;185    	unsigned char i;
;;;186    	
;;;187    	if(Addr>0x1f)													//ѡڲʱӣOSCIţVKL144B_ADDRWR5 bit0һҪ0
0001d4  2d1f              CMP      r5,#0x1f
0001d6  dd03              BLE      |L1.480|
;;;188    		i2cwrbuf[0]=VKL144B_ADDR5_1; 	//ѡⲿʱӣOSCIţVKL144B_ADDRWR5 bit0һҪ1
0001d8  20ec              MOVS     r0,#0xec
0001da  4983              LDR      r1,|L1.1000|
0001dc  7008              STRB     r0,[r1,#0]
0001de  e002              B        |L1.486|
                  |L1.480|
;;;189    	else                               
;;;190    		i2cwrbuf[0]=VKL144B_ADDR5_0; 
0001e0  20e8              MOVS     r0,#0xe8
0001e2  4981              LDR      r1,|L1.1000|
0001e4  7008              STRB     r0,[r1,#0]
                  |L1.486|
;;;191    	i2cwrbuf[1] = Addr&0x1f;
0001e6  f005001f          AND      r0,r5,#0x1f
0001ea  497f              LDR      r1,|L1.1000|
0001ec  7048              STRB     r0,[r1,#1]
;;;192    	for(i=0;i<cnt;i++)
0001ee  2400              MOVS     r4,#0
0001f0  e008              B        |L1.516|
                  |L1.498|
;;;193    	{
;;;194    		i2cwrbuf[2+i] = loopshift_left8(*Databuf++);  //ʾǵλ
0001f2  f8160b01          LDRB     r0,[r6],#1
0001f6  f7fffffe          BL       loopshift_left8
0001fa  1ca1              ADDS     r1,r4,#2
0001fc  4a7a              LDR      r2,|L1.1000|
0001fe  5450              STRB     r0,[r2,r1]
000200  1c60              ADDS     r0,r4,#1              ;192
000202  b2c4              UXTB     r4,r0                 ;192
                  |L1.516|
000204  42bc              CMP      r4,r7                 ;192
000206  dbf4              BLT      |L1.498|
;;;195    	}
;;;196    	txcnt = 0;
000208  2000              MOVS     r0,#0
00020a  4973              LDR      r1,|L1.984|
00020c  7008              STRB     r0,[r1,#0]
;;;197    	txlen=cnt+2;
00020e  1cb8              ADDS     r0,r7,#2
000210  4976              LDR      r1,|L1.1004|
000212  7008              STRB     r0,[r1,#0]
;;;198    	endflag = 0;
000214  2000              MOVS     r0,#0
000216  4973              LDR      r1,|L1.996|
000218  7008              STRB     r0,[r1,#0]
;;;199    
;;;200    	/* I2C function to write data to slave */
;;;201    	i2c0handlerflag = (I2C_FUNC)I2C_MasterTx;
00021a  f2af1029          ADR      r0,I2C_MasterTx + 1
00021e  496d              LDR      r1,|L1.980|
000220  6008              STR      r0,[r1,#0]  ; i2c0handlerflag
;;;202    
;;;203    	/* I2C as master sends START signal */
;;;204    	I2C_SET_CONTROL_REG(I2C0, I2C_CTL_STA);
000222  486b              LDR      r0,|L1.976|
000224  6800              LDR      r0,[r0,#0]
000226  f020003c          BIC      r0,r0,#0x3c
00022a  f0400020          ORR      r0,r0,#0x20
00022e  4968              LDR      r1,|L1.976|
000230  6008              STR      r0,[r1,#0]
;;;205    
;;;206    	/* Wait I2C Tx Finish */
;;;207    	while(endflag == 0);
000232  bf00              NOP      
                  |L1.564|
000234  486b              LDR      r0,|L1.996|
000236  7800              LDRB     r0,[r0,#0]  ; endflag
000238  2800              CMP      r0,#0
00023a  d0fb              BEQ      |L1.564|
;;;208    	endflag = 0;
00023c  2000              MOVS     r0,#0
00023e  4969              LDR      r1,|L1.996|
000240  7008              STRB     r0,[r1,#0]
;;;209    }
000242  bdf0              POP      {r4-r7,pc}
;;;210    
                          ENDP

                  VKL144B_I2C_RDDat PROC
;;;217    *******************************************************************************/
;;;218    void VKL144B_I2C_RDDat(unsigned char Addr,unsigned char *Databuf,unsigned char cnt)
000244  e92d41f0          PUSH     {r4-r8,lr}
;;;219    {	
000248  4605              MOV      r5,r0
00024a  460e              MOV      r6,r1
00024c  4617              MOV      r7,r2
;;;220    	unsigned char i,rxnum;
;;;221    	
;;;222    	rxnum=cnt;
00024e  46b8              MOV      r8,r7
;;;223    	for(i=0;i<rxnum;i++)
000250  2400              MOVS     r4,#0
000252  e038              B        |L1.710|
                  |L1.596|
;;;224    	{
;;;225    		//I2C͵ַ
;;;226    		if(Addr>0x1f)													//ѡڲʱӣOSCIţVKL144B_ADDRWR5 bit0һҪ0
000254  2d1f              CMP      r5,#0x1f
000256  dd03              BLE      |L1.608|
;;;227    		 i2crdtx[0]=VKL144B_ADDR5_1; 	//ѡⲿʱӣOSCIţVKL144B_ADDRWR5 bit0һҪ1
000258  20ec              MOVS     r0,#0xec
00025a  4960              LDR      r1,|L1.988|
00025c  7008              STRB     r0,[r1,#0]
00025e  e002              B        |L1.614|
                  |L1.608|
;;;228    	  else                               
;;;229    		 i2crdtx[0]=VKL144B_ADDR5_0; 
000260  20e8              MOVS     r0,#0xe8
000262  495e              LDR      r1,|L1.988|
000264  7008              STRB     r0,[r1,#0]
                  |L1.614|
;;;230    		i2crdtx[1]= (Addr&0x1f)+i;
000266  f005001f          AND      r0,r5,#0x1f
00026a  4420              ADD      r0,r0,r4
00026c  495b              LDR      r1,|L1.988|
00026e  7048              STRB     r0,[r1,#1]
;;;231    		txcnt = 0;
000270  2000              MOVS     r0,#0
000272  4959              LDR      r1,|L1.984|
000274  7008              STRB     r0,[r1,#0]
;;;232    		txlen=2;
000276  2002              MOVS     r0,#2
000278  495c              LDR      r1,|L1.1004|
00027a  7008              STRB     r0,[r1,#0]
;;;233    		endflag = 0;
00027c  2000              MOVS     r0,#0
00027e  4959              LDR      r1,|L1.996|
000280  7008              STRB     r0,[r1,#0]
;;;234    		//I2C
;;;235    	/* I2C function to read data from slave */
;;;236    		i2c0handlerflag = (I2C_FUNC)I2C_MasterRx;
000282  f2af205d          ADR      r0,I2C_MasterRx + 1
000286  4953              LDR      r1,|L1.980|
000288  6008              STR      r0,[r1,#0]  ; i2c0handlerflag
;;;237    
;;;238    		rxcnt = 0;
00028a  2000              MOVS     r0,#0
00028c  4958              LDR      r1,|L1.1008|
00028e  7008              STRB     r0,[r1,#0]
;;;239    		rxlen=1;
000290  2001              MOVS     r0,#1
000292  4958              LDR      r1,|L1.1012|
000294  7008              STRB     r0,[r1,#0]
;;;240    
;;;241    		I2C_SET_CONTROL_REG(I2C0, I2C_CTL_STA);
000296  484e              LDR      r0,|L1.976|
000298  6800              LDR      r0,[r0,#0]
00029a  f020003c          BIC      r0,r0,#0x3c
00029e  f0400020          ORR      r0,r0,#0x20
0002a2  494b              LDR      r1,|L1.976|
0002a4  6008              STR      r0,[r1,#0]
;;;242    
;;;243    		/* Wait I2C Rx Finish */
;;;244    		while(endflag == 0);
0002a6  bf00              NOP      
                  |L1.680|
0002a8  484e              LDR      r0,|L1.996|
0002aa  7800              LDRB     r0,[r0,#0]  ; endflag
0002ac  2800              CMP      r0,#0
0002ae  d0fb              BEQ      |L1.680|
;;;245    		*Databuf++=loopshift_left8(i2cwrbuf[txlen+i]); //ʾǵλȶ
0002b0  494e              LDR      r1,|L1.1004|
0002b2  7809              LDRB     r1,[r1,#0]  ; txlen
0002b4  4421              ADD      r1,r1,r4
0002b6  4a4c              LDR      r2,|L1.1000|
0002b8  5c50              LDRB     r0,[r2,r1]
0002ba  f7fffffe          BL       loopshift_left8
0002be  f8060b01          STRB     r0,[r6],#1
0002c2  1c60              ADDS     r0,r4,#1              ;223
0002c4  b2c4              UXTB     r4,r0                 ;223
                  |L1.710|
0002c6  4544              CMP      r4,r8                 ;223
0002c8  dbc4              BLT      |L1.596|
;;;246    	}
;;;247    }
0002ca  e8bd81f0          POP      {r4-r8,pc}
;;;248    /*******************************************************************************
                          ENDP

                  VKL144B_I2C_Cmd PROC
;;;255    *******************************************************************************/
;;;256    void VKL144B_I2C_Cmd(unsigned char* cmdbuf,unsigned char cnt)
0002ce  b510              PUSH     {r4,lr}
;;;257    {
;;;258    	unsigned char i;
;;;259    	
;;;260    	for(i=0;i<cnt;i++)
0002d0  2200              MOVS     r2,#0
0002d2  e005              B        |L1.736|
                  |L1.724|
;;;261    	{
;;;262    		i2cwrbuf[i] = *cmdbuf++;
0002d4  f8103b01          LDRB     r3,[r0],#1
0002d8  4c43              LDR      r4,|L1.1000|
0002da  54a3              STRB     r3,[r4,r2]
0002dc  1c53              ADDS     r3,r2,#1              ;260
0002de  b2da              UXTB     r2,r3                 ;260
                  |L1.736|
0002e0  428a              CMP      r2,r1                 ;260
0002e2  dbf7              BLT      |L1.724|
;;;263    	}
;;;264    	txcnt = 0;
0002e4  2300              MOVS     r3,#0
0002e6  4c3c              LDR      r4,|L1.984|
0002e8  7023              STRB     r3,[r4,#0]
;;;265    	txlen = cnt;
0002ea  4b40              LDR      r3,|L1.1004|
0002ec  7019              STRB     r1,[r3,#0]
;;;266    	endflag = 0;
0002ee  2300              MOVS     r3,#0
0002f0  4c3c              LDR      r4,|L1.996|
0002f2  7023              STRB     r3,[r4,#0]
;;;267    
;;;268    	/* I2C function to write data to slave */
;;;269    	i2c0handlerflag = (I2C_FUNC)I2C_MasterTx;
0002f4  f2af2305          ADR      r3,I2C_MasterTx + 1
0002f8  4c36              LDR      r4,|L1.980|
0002fa  6023              STR      r3,[r4,#0]  ; i2c0handlerflag
;;;270    
;;;271    	/* I2C as master sends START signal */
;;;272    	I2C_SET_CONTROL_REG(I2C0, I2C_CTL_STA);
0002fc  4b34              LDR      r3,|L1.976|
0002fe  681b              LDR      r3,[r3,#0]
000300  f023033c          BIC      r3,r3,#0x3c
000304  f0430320          ORR      r3,r3,#0x20
000308  4c31              LDR      r4,|L1.976|
00030a  6023              STR      r3,[r4,#0]
;;;273    
;;;274    	/* Wait I2C Tx Finish */
;;;275    	while(endflag == 0);
00030c  bf00              NOP      
                  |L1.782|
00030e  4b35              LDR      r3,|L1.996|
000310  781b              LDRB     r3,[r3,#0]  ; endflag
000312  2b00              CMP      r3,#0
000314  d0fb              BEQ      |L1.782|
;;;276    	endflag = 0;
000316  2300              MOVS     r3,#0
000318  4c32              LDR      r4,|L1.996|
00031a  7023              STRB     r3,[r4,#0]
;;;277    
;;;278    }
00031c  bd10              POP      {r4,pc}
;;;279    /*******************************************************************************
                          ENDP

                  main PROC
;;;285    *******************************************************************************/
;;;286    int main(void)
00031e  bf00              NOP      
000320  bf00              NOP      
000322  bf00              NOP      
                  |L1.804|
000324  2059              MOVS     r0,#0x59
000326  4934              LDR      r1,|L1.1016|
000328  6008              STR      r0,[r1,#0]
00032a  2016              MOVS     r0,#0x16
00032c  0589              LSLS     r1,r1,#22
00032e  f8c10100          STR      r0,[r1,#0x100]
000332  2088              MOVS     r0,#0x88
000334  f8c10100          STR      r0,[r1,#0x100]
000338  06c0              LSLS     r0,r0,#27
00033a  f8d00100          LDR      r0,[r0,#0x100]
00033e  2800              CMP      r0,#0
000340  d0f0              BEQ      |L1.804|
000342  bf00              NOP      
;;;287    {
;;;288    	/* Unlock protected registers */
;;;289    	SYS_UnlockReg();
;;;290    	SYS_Init();
000344  f7fffffe          BL       SYS_Init
;;;291    	/* Lock protected registers */
;;;292    	SYS_LockReg();
000348  bf00              NOP      
00034a  2000              MOVS     r0,#0
00034c  492a              LDR      r1,|L1.1016|
00034e  6008              STR      r0,[r1,#0]
000350  bf00              NOP      
;;;293    	
;;;294    	//PC15ΪPWMƵ32K
;;;295    	//Set Pwm mode as complementary mode
;;;296    	PWM_ENABLE_COMPLEMENTARY_MODE(PWM1);
000352  482a              LDR      r0,|L1.1020|
000354  6840              LDR      r0,[r0,#4]
000356  f04060e0          ORR      r0,r0,#0x7000000
00035a  4928              LDR      r1,|L1.1020|
00035c  6048              STR      r0,[r1,#4]
;;;297    	PWM_ConfigOutputChannel(PWM1, 0,32000, 50);//PWMƵ32KHzOSCIʱ
00035e  2332              MOVS     r3,#0x32
000360  f44f42fa          MOV      r2,#0x7d00
000364  2100              MOVS     r1,#0
000366  4825              LDR      r0,|L1.1020|
000368  f7fffffe          BL       PWM_ConfigOutputChannel
;;;298    	// Enable output of PWM1 channel 0
;;;299    	PWM_EnableOutput(PWM1, PWM_CH_0_MASK|PWM_CH_1_MASK);
00036c  2103              MOVS     r1,#3
00036e  4823              LDR      r0,|L1.1020|
000370  f7fffffe          BL       PWM_EnableOutput
;;;300    	PWM_Start(PWM1, 0x1);	
000374  2101              MOVS     r1,#1
000376  4821              LDR      r0,|L1.1020|
000378  f7fffffe          BL       PWM_Start
;;;301    	
;;;302    	//PD5(SCL),PD4(SDA)ΪӲI2C,Ƶ100khz
;;;303    	/* Open I2C module and set bus clock */
;;;304    	I2C_Open(I2C0, 30000);  //100khz
00037c  f2475130          MOV      r1,#0x7530
000380  4813              LDR      r0,|L1.976|
000382  f7fffffe          BL       I2C_Open
;;;305    	/* Set I2C Slave Addresses */
;;;306    	I2C_SetSlaveAddr(I2C0, 0, VKL144B_ADDR, 0);   
000386  2300              MOVS     r3,#0
000388  223e              MOVS     r2,#0x3e
00038a  4619              MOV      r1,r3
00038c  4810              LDR      r0,|L1.976|
00038e  f7fffffe          BL       I2C_SetSlaveAddr
;;;307    	/* Enable I2C interrupt */
;;;308    	I2C_EnableInt(I2C0);
000392  480f              LDR      r0,|L1.976|
000394  f7fffffe          BL       I2C_EnableInt
;;;309    	NVIC_EnableIRQ(I2C0_IRQn);
000398  2026              MOVS     r0,#0x26
00039a  f000021f          AND      r2,r0,#0x1f
00039e  2101              MOVS     r1,#1
0003a0  4091              LSLS     r1,r1,r2
0003a2  0942              LSRS     r2,r0,#5
0003a4  0092              LSLS     r2,r2,#2
0003a6  f10222e0          ADD      r2,r2,#0xe000e000
0003aa  f8c21100          STR      r1,[r2,#0x100]
0003ae  bf00              NOP      
;;;310    		
;;;311    	VKL144B_Main();
0003b0  f7fffffe          BL       VKL144B_Main
;;;312    	
;;;313    	while(1)
0003b4  bf00              NOP      
                  |L1.950|
0003b6  e7fe              B        |L1.950|
;;;314    	{					
;;;315    	}
;;;316    }	
;;;317    /************************END OF FILE****/
                          ENDP

                  I2C_STOP PROC
;;;367     */
;;;368    static __INLINE void I2C_STOP(I2C_T *i2c)
0003b8  6801              LDR      r1,[r0,#0]
;;;369    {
;;;370    
;;;371        (i2c)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk);
0003ba  f0410118          ORR      r1,r1,#0x18
0003be  6001              STR      r1,[r0,#0]
;;;372        while(i2c->CTL & I2C_CTL_STO_Msk);
0003c0  bf00              NOP      
                  |L1.962|
0003c2  6801              LDR      r1,[r0,#0]
0003c4  f0010110          AND      r1,r1,#0x10
0003c8  2900              CMP      r1,#0
0003ca  d1fa              BNE      |L1.962|
;;;373    }
0003cc  4770              BX       lr
;;;374    
                          ENDP

0003ce  0000              DCW      0x0000
                  |L1.976|
                          DCD      0x40080000
                  |L1.980|
                          DCD      i2c0handlerflag
                  |L1.984|
                          DCD      txcnt
                  |L1.988|
                          DCD      i2crdtx
                  |L1.992|
                          DCD      i2crdrx
                  |L1.996|
                          DCD      endflag
                  |L1.1000|
                          DCD      i2cwrbuf
                  |L1.1004|
                          DCD      txlen
                  |L1.1008|
                          DCD      rxcnt
                  |L1.1012|
                          DCD      rxlen
                  |L1.1016|
                          DCD      0x40000100
                  |L1.1020|
                          DCD      0x40059000

                          AREA ||.bss||, DATA, NOINIT, ALIGN=0

                  i2cwrbuf
                          %        64
                  i2crdtx
                          %        64

                          AREA ||.data||, DATA, ALIGN=2

                  i2c0handlerflag
                          DCD      0x00000000
                  i2crdrx
000004  00                DCB      0x00
                  rxdummy
000005  00                DCB      0x00
                  txlen
000006  00                DCB      0x00
                  txcnt
000007  00                DCB      0x00
                  rxlen
000008  00                DCB      0x00
                  rxcnt
000009  00                DCB      0x00
                  endflag
00000a  00                DCB      0x00

;*** Start embedded assembler ***

#line 1 "..\\User\\main.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___6_main_c_endflag____REV16|
#line 114 "..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___6_main_c_endflag____REV16| PROC
#line 115

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___6_main_c_endflag____REVSH|
#line 128
|__asm___6_main_c_endflag____REVSH| PROC
#line 129

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***

                  __ARM_use_no_argv EQU 0
